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公开(公告)号：US20220262953A1
公开(公告)日：2022-08-18
申请号：US17628091
申请日：2020-07-27
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Munehiro KOZUMA , Takahiko ISHIZU , Takeshi AOKI , Masashi FUJITA , Kazuma FURUTANI , Kousuke SASAKI
IPC: H01L29/786 , H01L27/108 , G11C7/10 , G11C7/12 , G11C7/14 , G06F7/544
Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
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公开(公告)号：US20210265504A1
公开(公告)日：2021-08-26
申请号：US17053467
申请日：2019-05-07
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takahiko ISHIZU , Kazuma FURUTANI
IPC: H01L29/786 , G11C11/405 , H01L27/108 , G11C5/06 , G11C11/4096 , G11C11/4093
Abstract: A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.
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公开(公告)号：US20150241510A1
公开(公告)日：2015-08-27
申请号：US14625984
申请日：2015-02-19
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Masashi TSUBUKU , Kazuma FURUTANI , Atsushi HIROSE , Toshihiko TAKEUCHI
CPC classification number: G01R19/0092
Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g., a difference between the third potential and the fourth potential), and a value of current flowing between the first terminal of the transistor under test and the second terminal of the first transistor is calculated from the amount of the charge held by the node.
Abstract translation: 提供了一个微小的电流测量方法。 在当前的测量方法中，将第一电位施加到被测晶体管的第一端，将第二电位施加到第一晶体管的第一端，第一晶体管导通以在节点中积累预定电荷 将被测晶体管的第二端与第一晶体管的第二端连接，测量与节点电连接的读取电路的输出端的第三电位，第一晶体管截止，输出的第四电位 测量与节点电连接的读取电路的端子，根据读取电路的输出端子的电位变化量来估计由节点保持的电荷量（例如，第三电位与 第四电位），并且计算在被测晶体管的第一端子与第一晶体管的第二端子之间流动的电流值 d由节点持有的费用量。
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公开(公告)号：US20240363069A1
公开(公告)日：2024-10-31
申请号：US18685010
申请日：2022-08-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Kouhei TOYOTAKA , Kazuma FURUTANI
CPC classification number: G09G3/3233 , G09G3/2074 , H10K71/70 , G09G2354/00 , G09G2360/10 , G09G2360/142 , G09G2360/148 , H10K39/34 , H10K59/13 , H10K59/40
Abstract: A novel correction method for a display apparatus is provided. A correction circuit of the display apparatus obtains offset corresponding to a current flowing through a second subpixel when a first subpixel is not lit. The correction circuit of the display apparatus obtains, for each pixel, correction output data, obtained by correcting, with the offset, data corresponding to a current flowing through each of the second subpixels in sequentially supplying correction video data to the first subpixels and stores the correction video data and the correction output data corresponding to the correction video data in a memory circuit. The correction circuit of the display apparatus calculates coefficients obtained when a relation between the correction video data and the correction output data corresponding to the correction video data is approximated by a quadratic expression and stores the coefficients in the memory circuit. The correction circuit of the display apparatus stores a correction table that is created on the basis of the correction output data and the coefficients, in the memory circuit. The correction circuit of the display apparatus corrects display video data in accordance with the correction table.
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公开(公告)号：US20230363174A1
公开(公告)日：2023-11-09
申请号：US18245757
申请日：2021-09-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Shunpei YAMAZAKI , Yasuhiro JINBO , Hitoshi KUNITAKE , Kazuaki OHSHIMA , Masashi OOTA , Kazuma FURUTANI , Takeshi AOKI
IPC: H10B51/30 , H10B53/30 , H01L29/786 , H01L29/417 , H01L29/78
CPC classification number: H10B51/30 , H10B53/30 , H01L29/7869 , H01L29/41733 , H01L29/78696 , H01L29/78391
Abstract: A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.
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Patent Agency Ranking
公开(公告)号：US20220392925A1
公开(公告)日：2022-12-08
申请号：US17774958
申请日：2020-11-05
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takahiko ISHIZU , Kazuma FURUTANI , Takayuki IKEDA
IPC: H01L27/12 , H01L29/786
Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a memory circuit including a first transistor and a second transistor. The first transistor is formed on a silicon substrate. The second transistor is formed in a layer above a layer where the first transistor is provided. The first transistor includes a first gate electrode and a first back gate electrode with a first channel formation region interposed therebetween. The first gate electrode is electrically connected to one of a source and a drain of the second transistor. The first back gate electrode is formed using a region where an impurity element imparting a conductivity type is selectively introduced in the silicon substrate. The second transistor includes a second channel formation region. The second channel formation region includes a metal oxide.
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公开(公告)号：US20250158621A1
公开(公告)日：2025-05-15
申请号：US18834518
申请日：2023-02-13
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Kazuaki OHSHIMA , Yoshiyuki KUROKAWA , Kazuma FURUTANI
Abstract: A novel semiconductor device or the like is provided. The semiconductor device that includes a first flip-flop having a function of retaining input data in response to a clock signal and outputting first output data based on the input data; a second flip-flop having a function of retaining the input data in response to the clock signal and outputting second output data based on the input data; a third flip-flop having a function of retaining the input data in response to the clock signal and outputting third output data based on the input data; a majority circuit to which the first output data to the third output data are input and having a function of determining the most common logical value in the first output data to the third output data by majority decision making and outputting data of the determined logical value as fourth output data; and a switching circuit to which the first output data and the fourth output data are input and having a function of outputting output data based on the first output data or the fourth output data in response to a switching signal.
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公开(公告)号：US20250147841A1
公开(公告)日：2025-05-08
申请号：US18835451
申请日：2023-02-08
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Kazuma FURUTANI , Yoshiyuki KUROKAWA , Kazuaki OHSHIMA , Hideki UOCHI
IPC: G06F11/10
Abstract: A highly reliable memory device is provided. Of an information bit and a check bit forming a hamming code, the information bit having a larger bit length than the check bit is stored in a first memory portion, and the check bit is stored in the second memory portion. The hamming code is divided and stored in a plurality of memory portions, whereby occurrence of a soft error is suppressed. The first memory portion that needs a large memory capacity is formed using a Si transistor, and the second memory portion is formed using an OS transistor. A combination of memory scribing and bit interleaving achieves a highly reliable memory device.
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公开(公告)号：US20240411134A1
公开(公告)日：2024-12-12
申请号：US18698873
申请日：2022-10-06
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Masashi FUJITA , Yoshiyuki KUROKAWA , Hiromichi GODO , Seiko INOUE , Kazuma FURUTANI , Kouhei TOYOTAKA
IPC: G02B27/01 , G02B27/00 , H04N13/344 , H04N13/383
Abstract: An optical device of the present invention includes a display apparatus (10) and an optical system (12). The display apparatus (10) includes a display region (60) and a sensor region (52). The optical system (12) includes a first mirror (21) and a second mirror (22). The first mirror (21) includes a first surface and a second surface. The display region (60) has a function of emitting first light (31). The first mirror (21) is provided on an optical path of the first light (31) and has a function of transmitting the first light (31) incident on the first surface to the second surface and a function of reflecting second light (33) incident on the second surface. The second mirror (22) is provided on an optical path of the second light (33) and has a function of reflecting the second light (33). The sensor region (52) has a function of detecting the second light (33) via the first mirror (21) and the second mirror (22).
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公开(公告)号：US20220209016A1
公开(公告)日：2022-06-30
申请号：US17694787
申请日：2022-03-15
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takahiko ISHIZU , Kazuma FURUTANI
IPC: H01L29/786 , G11C5/06 , G11C11/405 , G11C11/4093 , G11C11/4096 , H01L27/108
Abstract: A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.
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