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公开(公告)号：US20180088422A1
公开(公告)日：2018-03-29
申请号：US15123064
申请日：2016-04-28
Inventor： Hui Xia , Tienchun Huang
IPC: G02F1/1362 , H01L27/12 , G02F1/1335 , G02F1/1343 , H01L21/77
CPC classification number: G02F1/136227 , G02F1/1335 , G02F1/1343 , G02F1/136277 , G02F1/1368 , G02F2001/133357 , H01L21/77 , H01L27/12 , H01L27/124
Abstract: An array substrate and a manufacturing method thereof are disclosed. The array substrate includes: a glass substrate; a gate electrode; a first insulating layer; a semiconductor layer; a planarization layer mounted on the first insulating layer; a source electrode and a drain electrode; a pixel electrode layer mounted on the planarization layer and the drain electrode; a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode. The array substrate can prevent bubbles from forming at through holes and thereby increasing aperture ratio. The planarization layer further increases distances between the source electrode, the drain electrode and the gate electrode, which enhances antistatic ability.
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公开(公告)号：US10120252B2
公开(公告)日：2018-11-06
申请号：US15123064
申请日：2016-04-28
Inventor： Hui Xia , Tienchun Huang
IPC: H01L31/072 , G02F1/1362 , G02F1/1368 , H01L21/77 , H01L27/12 , G02F1/1335 , G02F1/1343 , G02F1/1333
Abstract: An array substrate and a manufacturing method thereof are disclosed. The array substrate includes: a glass substrate; a gate electrode; a first insulating layer; a semiconductor layer; a planarization layer mounted on the first insulating layer; a source electrode and a drain electrode; a pixel electrode layer mounted on the planarization layer and the drain electrode; a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode. The array substrate can prevent bubbles from forming at through holes and thereby increasing aperture ratio. The planarization layer further increases distances between the source electrode, the drain electrode and the gate electrode, which enhances antistatic ability.
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公开(公告)号：US10120246B2
公开(公告)日：2018-11-06
申请号：US15328495
申请日：2016-12-15
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L21/00 , G02F1/1343 , H01L21/77 , H01L27/12 , G02F1/1333 , G02F1/1335 , G02F1/1362 , G02F1/1368
Abstract: The present invention provides a manufacturing method of an IPS array substrate and an IPS array substrate. The manufacturing method of the IPS array substrate according to the present invention uses a half-tone mask to simultaneously form a common electrode and a pixel electrode that stagger in a longitudinal direction so that the common electrode is set inside a common electrode channel of an insulation protection layer while the pixel electrode is set on an upper surface of the insulation protection layer to provide an IPS array substrate, which, compared to a traditional IPS array substrate, allows the common electrode and the pixel electrode to generate therebetween a longitudinal component of an electric field whereby liquid crystal of a liquid crystal panel that is located above the pixel electrode can be driven and used, where the liquid crystal is allowed to rotate horizontally and also allowed to generate a predetermined longitudinal tilt angle the TFT substrate can be a TFT substrate provided for a traditional IPS array substrate, making it possible to save one mask and associated process, as compared to a traditional FFS array substrate, and thus saving manufacturing cost.
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公开(公告)号：US10461097B2
公开(公告)日：2019-10-29
申请号：US15115254
申请日：2016-07-11
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L29/04 , H01L27/12 , H01L21/77 , G02F1/1362 , G02F1/1368 , H01L21/02 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786 , G02F1/1343
Abstract: The present application discloses an array substrate and a method of manufacturing the same. The array substrate includes a first insulating layer disposed on the substrate; a source electrode pattern disposed within the first insulating layer; an annular gate electrode pattern disposed on the first insulating layer and surrounded the periphery of the source electrode pattern; a second insulating layer covering on the annular gate electrode pattern; a semiconductor pattern disposed in the annular area of the annular gate electrode pattern, and is electrically connected to the exposed portion of the source electrode pattern, the semiconductor pattern is further electrical insulation to the annular gate electrode pattern through the second insulating layer; a pixel electrode disposed on the second insulating layer and electrically connected to a side of the semiconductor pattern remote from the substrate.
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公开(公告)号：US10297692B2
公开(公告)日：2019-05-21
申请号：US15115914
申请日：2016-06-23
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L29/786 , H01L21/02 , H01L21/027 , H01L21/28 , H01L21/285 , H01L21/306 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L21/443 , H01L21/467 , H01L21/4757 , H01L21/4763 , H01L23/31 , H01L27/12 , H01L29/49 , H01L29/66
Abstract: The invention provides a manufacturing method of TFT substrate and a TFT substrate. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.
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Patent Agency Ranking
公开(公告)号：US10249648B2
公开(公告)日：2019-04-02
申请号：US15117446
申请日：2016-07-20
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L27/12 , G02F1/1368 , H01L21/77
Abstract: The present disclosure relates to an array substrate and the manufacturing method thereof. The manufacturing method includes the steps including: forming a buffer layer on a substrate, forming a source and a data line within the buffer layer, and forming a gate and a gate line on the buffer layer, forming an insulation layer on the source, the data line, the gate, and the gate line, forming a semiconductor layer on the source, and forming a first pixel electrode and a second pixel electrode on the insulation layer. The manufacturing efficiency of the manufacturing process of the array substrate is high, and the manufacturing process is also energy saving.
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公开(公告)号：US20180108782A1
公开(公告)日：2018-04-19
申请号：US15115914
申请日：2016-06-23
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L29/786 , H01L27/12 , H01L23/31 , H01L21/285 , H01L21/027 , H01L21/306 , H01L29/66 , H01L21/02 , H01L21/311 , H01L29/49 , H01L21/443 , H01L21/3213 , H01L21/4763 , H01L21/308 , H01L21/467 , H01L21/28 , H01L21/4757
CPC classification number: H01L29/78642 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/0274 , H01L21/28158 , H01L21/28568 , H01L21/30604 , H01L21/3081 , H01L21/31111 , H01L21/31144 , H01L21/32134 , H01L21/32139 , H01L21/443 , H01L21/467 , H01L21/47573 , H01L21/47635 , H01L23/3171 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1262 , H01L27/127 , H01L27/1288 , H01L29/4908 , H01L29/66742 , H01L29/6675 , H01L29/66969 , H01L29/78648
Abstract: The invention provides a manufacturing method of TFT substrate and a TFT substrate. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.
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公开(公告)号：US11114567B2
公开(公告)日：2021-09-07
申请号：US16278718
申请日：2019-02-19
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L29/786 , H01L29/66 , H01L21/02 , H01L21/027 , H01L21/28 , H01L21/285 , H01L21/306 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L21/443 , H01L21/467 , H01L21/4757 , H01L21/4763 , H01L23/31 , H01L27/12 , H01L29/49
Abstract: A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.
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公开(公告)号：US20190181272A1
公开(公告)日：2019-06-13
申请号：US16278718
申请日：2019-02-19
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L29/786 , H01L29/66 , H01L21/28 , H01L21/285 , H01L21/443 , H01L23/31 , H01L27/12 , H01L21/02 , H01L21/027 , H01L21/306 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L21/467 , H01L21/4757 , H01L21/4763 , H01L29/49
Abstract: A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.
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公开(公告)号：US10193089B2
公开(公告)日：2019-01-29
申请号：US15123641
申请日：2016-07-06
Inventor： Zhichao Zhou , Hui Xia
IPC: H01L27/12 , H01L51/05 , H01L27/32 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786
Abstract: A display device, an array substrate, and a manufacturing method for the array substrate are disclosed. The array substrate includes a substrate base, and two gates, a source, a drain, an active layer, and a pixel electrode on the substrate base. The drain and the pixel electrode are connected together. The source and the drain contact the active layer, respectively. The two gates control the conduction and cut off of the active layer, which in turn controls the conduction and cut off between the source and the drain. Through the present disclosure, the variation of threshold voltage is effectively prevented.
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