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    Integrated Circuit Assembly with Faraday Cage
    5.
    发明申请
    Integrated Circuit Assembly with Faraday Cage 有权
    集成电路组件与法拉第笼

    公开(公告)号：US20150137307A1

    公开(公告)日：2015-05-21

    申请号：US14596515

    申请日：2015-01-14

    Applicant: Silanna Semiconductor U.S.A., Inc.

    Inventor： Michael A. Stuber

    IPC: H01L21/768 ,  H01L23/60 ,  H01L23/48

    CPC classification number: H01L23/60 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer. The third electrically conductive interconnect layer forms a second electrically conductive plate below the electrically conductive ring and the region of the semiconductor layer. The plurality of electrically conductive vias electrically couple the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate. The electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device.

    Abstract translation: 集成电路组件形成有绝缘层，半导体层，有源器件，第一，第二和第三导电互连层以及多个导电通孔。 绝缘层具有第一表面和第二表面。 第二个表面位于第一个表面之下。 衬底层已经从第二表面去除。 半导体层具有第一表面和第二表面。 半导体层的第一表面接触绝缘层的第一表面。 有源器件形成在半导体层的区域中。 第一导电互连层形成导电环。 第二导电互连层在导电环和半导体层的区域之上形成第一导电板。 第三导电互连层在导电环和半导体层的区域之下形成第二导电板。 多个导电通孔将导电环电耦合到第一导电板和第二导电板。 导电环，第一导电板，第二导电板和多个导电通孔围绕有源器件形成法拉第笼。

    EMI SHIELD FOR HIGH FREQUENCY LAYER TRANSFERRED DEVICES
    6.
    发明申请
    EMI SHIELD FOR HIGH FREQUENCY LAYER TRANSFERRED DEVICES 有权
    用于高频层传输设备的EMI屏蔽

    公开(公告)号：US20160043044A1

    公开(公告)日：2016-02-11

    申请号：US14454204

    申请日：2014-08-07

    Applicant: Silanna Semiconductor U.S.A., Inc.

    Inventor： Michael A. Stuber

    IPC: H01L23/60 ,  H01L21/84 ,  H01L21/768

    CPC classification number: H01L23/60 ,  H01L21/6835 ,  H01L21/76256 ,  H01L21/76838 ,  H01L21/78 ,  H01L21/84 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor.

    Abstract translation: 公开了涉及用于射频层转移装置的EMI屏蔽的各种方法和装置。 一种方法包括在绝缘体上半导体晶片的有源层中形成射频场效应晶体管。 绝缘体上半导体晶片具有掩埋绝缘体侧和有源层侧。 该方法还包括将第二晶片接合到绝缘体上半导体晶片的有源层侧。 该方法还包括形成半导体器件的屏蔽层。 屏蔽层包括导电材料。 该方法还包括将射频场效应晶体管耦合到包括射频分量的电路。 该方法还包括将射频场效应晶体管，射频分量和屏蔽层分成模具。 屏蔽层位于射频成分的基板和射频场效应晶体管之间。

    Semiconductor-on-Insulator Integrated Circuit with Reduced Off-State Capacitance
    9.
    发明申请
    Semiconductor-on-Insulator Integrated Circuit with Reduced Off-State Capacitance 有权
    具有降低断态电容的绝缘体半导体集成电路

    公开(公告)号：US20140327077A1

    公开(公告)日：2014-11-06

    申请号：US14335906

    申请日：2014-07-19

    Applicant: Silanna Semiconductor U.S.A., Inc.

    Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Chris Brindle

    IPC: H01L27/12 ,  H01L23/48

    CPC classification number: H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other.

    Abstract translation: 集成电路组件包括绝缘层，半导体层，手柄层，金属互连层和晶体管。 绝缘层具有第一表面，第二表面和从第一表面延伸到第二表面的孔。 半导体层具有第一表面和第二表面，半导体层的第一表面与绝缘层的第一表面接触。 手柄层耦合到半导体层的第二表面。 金属互连层耦合到绝缘层的第二表面，金属互连层设置在绝缘层的孔内。 晶体管位于半导体层中。 绝缘层中的孔至少延伸到半导体层的第一表面。 金属互连层将多个晶体管彼此电耦合。

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