公开(公告)号：US20140319698A1

公开(公告)日：2014-10-30

申请号：US14326304

申请日：2014-07-08

Applicant: Silanna Semiconductor U.S.A., Inc.

Inventor： Stuart B. Molin ,  Michael A. Stuber ,  Mark Drucker

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/2007 ,  H01L21/3221 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/13

Abstract: A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer.

Abstract translation: 半导体结构形成有第一和第二半导体晶片和再分配层。 第一半导体晶片形成有第一有源层和第一互连层。 第二半导体晶片形成有第二有源层和第二互连层。 第二半导体晶片被倒置并结合到第一半导体晶片，并且从第二半导体晶片去除衬底。 再分布层在第二半导体晶片的一侧重新分布电连接焊盘位置。 再分配层还通过第二有源层和第二互连层中的孔与第一互连层电接触。

公开(公告)号：US20150140782A1

公开(公告)日：2015-05-21

申请号：US14572580

申请日：2014-12-16

Applicant: Silanna Semiconductor U.S.A., Inc.

Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Mark Drucker ,  Peter Fowler

IPC: H01L21/762 ,  H01L21/84

CPC classification number: H01L21/76251 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48666 ,  H01L2224/48684 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48766 ,  H01L2224/48784 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48866 ,  H01L2224/48884 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80048 ,  H01L2224/80896 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/831 ,  H01L2224/8382 ,  H01L2224/8385 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/1144 ,  H01L2924/00012 ,  H01L2224/83205 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Abstract translation: 集成电路组件包括具有第一表面和第二表面的绝缘层。 第一有源层接触绝缘层的第一表面。 金属接合焊盘与第一有源层电连接并形成在绝缘层的第二表面上。 提供具有第一表面和第二表面的衬底，其中形成在第一表面中的第二有源层使得第一有源层耦合到衬底的第二表面。

公开(公告)号：US20150108640A1

公开(公告)日：2015-04-23

申请号：US14586668

申请日：2014-12-30

Applicant: Silanna Semiconductor U.S.A., Inc.

Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Mark Drucker ,  Peter Fowler

IPC: H01L23/00

CPC classification number: H01L21/76251 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48666 ,  H01L2224/48684 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48766 ,  H01L2224/48784 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48866 ,  H01L2224/48884 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80048 ,  H01L2224/80896 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/831 ,  H01L2224/8382 ,  H01L2224/8385 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/1144 ,  H01L2924/00012 ,  H01L2224/83205 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.

Abstract translation: 集成电路组件包括具有第一表面和第二表面的绝缘层，其中绝缘层的第一表面低于集成电路组件的上平面以下10微米。 有源层接触绝缘层的第一表面。 金属接合焊盘与有源层电连接并形成在绝缘层的第二表面上，并且还与印刷电路板电连接。 制造集成电路组件的方法包括将处理晶片耦合到绝缘体上半导体晶片的有源层，去除绝缘体上半导体的衬底，形成连接到暴露绝缘体上的有源层的接合焊盘 表面，使用焊料凸块将接合焊盘接合到印刷电路板上，以及去除处理晶片。