公开(公告)号：US20140187037A1

公开(公告)日：2014-07-03

申请号：US13844915

申请日：2013-03-16

Applicant: SK HYNIX INC.

Inventor： Il-Cheol RHO ,  Jong-Min LEE

IPC: H01L29/92 ,  H01L21/764

CPC classification number: H01L21/7682 ,  H01L21/28008 ,  H01L21/764 ,  H01L21/76877 ,  H01L21/76886 ,  H01L27/10823 ,  H01L27/10855 ,  H01L29/92

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成多个半导体结构，在半导体结构上形成层间电介质层，蚀刻层间电介质层，并且在半导体结构之间限定开放部分以露出衬底的表面， 在开放部分的侧壁上形成牺牲隔离物，在开放部分中形成导电层图案，并使导电层图案和牺牲间隔物彼此到达，并且在开口部分的侧壁上限定气隙。

公开(公告)号：US20150132936A1

公开(公告)日：2015-05-14

申请号：US14604438

申请日：2015-01-23

Applicant: SK hynix Inc.

Inventor： Il-Cheol RHO ,  Jong-Min LEE

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/7682 ,  H01L21/28008 ,  H01L21/764 ,  H01L21/76877 ,  H01L21/76886 ,  H01L27/10823 ,  H01L27/10855 ,  H01L29/92

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成多个半导体结构，在半导体结构上形成层间电介质层，蚀刻层间电介质层，并且在半导体结构之间限定开放部分以露出衬底的表面， 在开放部分的侧壁上形成牺牲隔离物，在开放部分中形成导电层图案，并使导电层图案和牺牲间隔物彼此到达，并且在开口部分的侧壁上限定气隙。