公开(公告)号：US20170052577A1

公开(公告)日：2017-02-23

申请号：US14962260

申请日：2015-12-08

Applicant: SK hynix Inc.

Inventor： Kwang-Su KIM

IPC: G06F1/24 ,  G06F1/32 ,  G06F9/44 ,  G06F3/06

CPC classification number: G06F9/4418 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0652 ,  G06F3/0673 ,  Y02D10/14 ,  Y02D10/171

Abstract: A memory system may include: a memory device that operates using a first voltage received from a host and suitable for storing a value of operation information, and waking up from a sleep state in response to a request of the host; and a controller that operates using a second voltage received from the host, and suitable for selectively resetting the memory device according to a result obtained by checking a value of operation information of the memory device, when waking up the memory device in a sleep state according to a request of the host.

Abstract translation: 存储器系统可以包括：存储器装置，其使用从主机接收的适合于存储操作信息的值的第一电压并响应于主机的请求从休眠状态唤醒; 以及控制器，其使用从主机接收到的第二电压进行操作，并且适于根据通过检查存储器件的操作信息的值获得的结果来选择性地重置存储器件，当按照睡眠状态唤醒存储器件时 以主机的请求。

公开(公告)号：US20210149597A1

公开(公告)日：2021-05-20

申请号：US16849469

申请日：2020-04-15

Applicant: SK hynix Inc.

Inventor： Kwang-Su KIM

IPC: G06F3/06

Abstract: A controller for controlling a memory device may include: a sequence detector suitable for determining, each time a set number of data chunks are processed, whether the set number of recently processed data chunks are sequential data chunks, based on the lengths of the data chunks and logical-address-adjacency of the data chunks; and a processor suitable for performing a sequential operation according to the determination result, until next determination.

公开(公告)号：US20170185463A1

公开(公告)日：2017-06-29

申请号：US15179347

申请日：2016-06-10

Applicant: SK hynix Inc.

Inventor： Kwang-Su KIM ,  Jong-Min LEE

IPC: G06F11/07 ,  G06F11/10 ,  G11C29/50 ,  G11C29/42

CPC classification number: G06F11/076 ,  G06F11/1048 ,  G06F11/1072 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50004 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0409

Abstract: An operating method of a memory system including a plurality of memory blocks may include grouping the pages of a selected memory block among the plurality of memory blocks based on a program time, sequentially performing a test read on the groups of the pages, detecting an error in the pages of the test-read groups, and reprogramming a page selected based on a result of the error detection.