公开(公告)号：US09053776B2

公开(公告)日：2015-06-09

申请号：US13672493

申请日：2012-11-08

Applicant: SK hynix Inc.

Inventor： Kwanweon Kim ,  Hyunsu Yoon ,  Jeongtae Hwang

IPC: G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C2029/4402

Abstract: A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.

Abstract translation: 设置信息存储电路包括：第一解码器，被配置为分别响应于选择代码和第一设置信号产生第一输入使能信号，第一寄存器组分别被配置为对应于第一解码器，并且在第一输入时接收设置数据 使能分别对应于第一寄存器组的第一解码器产生的信号，并且存储所接收的设置数据，第二解码器被配置为分别响应于选择代码产生第二输入使能信号，第二组 信号和第二寄存器组，分别被配置为对应于第二解码器，并且当分别对应于第二寄存器组的第二解码器产生的第二输入使能信号被使能时接收设置数据，并存储接收的设置 数据。