公开(公告)号：US11094369B1

公开(公告)日：2021-08-17

申请号：US16928192

申请日：2020-07-14

Applicant: SK hynix Inc.

Inventor： Nogeun Joo ,  Jungho Lim ,  Byeongchan Choi ,  Jeongtae Hwang

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10

Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command.