公开(公告)号：US09209146B2

公开(公告)日：2015-12-08

申请号：US14532393

申请日：2014-11-04

Applicant: SK hynix Inc.

Inventor： Seung Jee Kim ,  Qwan Ho Chung ,  Jong Hyun Nam ,  Si Han Kim ,  Sang Yong Lee ,  Seong Cheol Shin

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/02333 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03334 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/03474 ,  H01L2224/03903 ,  H01L2224/03906 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11602 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.

Abstract translation: 电子器件封装包括具有设置在半导体芯片的接触部分上的柱和从柱的上部侧向突出的扩大部分的凸块; 互连部分，其具有基本上围绕所述柱的扩大部分和上侧壁的锁定部分; 以及基本上围绕所述凸起和所述锁定部分的绝缘层，以将所述互连部分与所述半导体芯片分离。

公开(公告)号：US09099313B2

公开(公告)日：2015-08-04

申请号：US13846807

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Si Han Kim

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K1/18 ,  H05K3/12 ,  H05K3/18 ,  H05K3/46

CPC classification number: H01L24/03 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92132 ,  H01L2224/92244 ,  H01L2924/12042 ,  H05K1/185 ,  H05K3/12 ,  H05K3/18 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embedded package in which active elements, such as semiconductor chips, are embedded within a package substrate. The semiconductor chips, embedded within a dielectric layer, are coupled with circuit wires to ensure electrical and signal continuity. When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized.

Abstract translation: 嵌入式封装，其中诸如半导体芯片的有源元件嵌入在封装衬底内。 嵌入在介电层内的半导体芯片与电路线耦合以确保电气和信号的连续性。 当在不同的方向上进行半导体芯片和封装基板之间的连接时，总的互连面积减小，连接可靠性提高，泄漏电流降低，并且可以实现更高的器件产量。

公开(公告)号：US09209150B2

公开(公告)日：2015-12-08

申请号：US14085357

申请日：2013-11-20

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Qwan Ho Chung ,  Seung Jee Kim ,  Jong Hyun Nam ,  Si Han Kim

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/25 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. The first insulation layer has a trench disposed in a portion of the first insulation layer to expose the plurality of bumps.

Abstract translation: 提供嵌入式软件包。 嵌入式封装包括附着到芯层的第一表面的芯片，与芯层相对的芯片表面上的多个凸起，以及围绕芯层，芯片和多个凸块的第一绝缘层。 第一绝缘层具有设置在第一绝缘层的一部分中以暴露多个凸块的沟槽。

公开(公告)号：US08680652B2

公开(公告)日：2014-03-25

申请号：US13687056

申请日：2012-11-28

Applicant: SK Hynix Inc.

Inventor： Si Han Kim ,  Myung Geun Park

IPC: H01L21/02 ,  H01L23/48

CPC classification number: H01L29/92 ,  H01L27/0805 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00014

Abstract: A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

Abstract translation: 堆叠封装包括第一半导体芯片第一焊盘和设置在其上的第二焊盘，以及具有第三焊盘的第二半导体芯片和与其上设置的第二焊盘电连接的第四焊盘。 电容器介于第一半导体芯片和第二半导体芯片之间，并且包括与第一半导体芯片的第一焊盘电连接的第一电极，与第二半导体芯片的第三焊盘电连接的第二电极，以及介于第一半导体芯片之间的电介质 电极和第二电极。