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公开(公告)号：US09419748B2
公开(公告)日：2016-08-16
申请号：US14454057
申请日：2014-08-07
Applicant: SK hynix memory solutions inc.
Inventor： Kwok W. Yeung , Kin Man Ng , Kin Ming Chan
CPC classification number: H04L1/004 , G06F11/10 , H03M13/1111 , H03M13/2933 , H03M13/3715 , H03M13/3738 , H03M13/4138 , H03M13/6502 , H03M13/6508 , H04L1/005 , H04L1/0053
Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.
Abstract translation: 公开了一种用于对解码器进行计时的系统。 该系统包括：被配置为接收输入数据的通道前端，被配置为提供作为到通道前端的输入的第一时钟信号的第一时钟，被配置为接收与通道前端的输出相关联的中间数据的解码器，以及 第二时钟，被配置为提供第二时钟信号作为解码器的输入。 在一些实施例中，第二时钟信号不是从第一时钟信号导出的。
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公开(公告)号：US20150033093A1
公开(公告)日：2015-01-29
申请号：US14454057
申请日：2014-08-07
Applicant: SK Hynix memory solutions inc.
Inventor： Kwok W. Yeung , Kin Man Ng , Kin Ming Chan
CPC classification number: H04L1/004 , G06F11/10 , H03M13/1111 , H03M13/2933 , H03M13/3715 , H03M13/3738 , H03M13/4138 , H03M13/6502 , H03M13/6508 , H04L1/005 , H04L1/0053
Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.
Abstract translation: 公开了一种用于对解码器进行计时的系统。 该系统包括：被配置为接收输入数据的通道前端，被配置为提供作为到通道前端的输入的第一时钟信号的第一时钟，被配置为接收与通道前端的输出相关联的中间数据的解码器，以及 第二时钟，被配置为提供第二时钟信号作为解码器的输入。 在一些实施例中，第二时钟信号不是从第一时钟信号导出的。
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公开(公告)号：US09529744B2
公开(公告)日：2016-12-27
申请号：US14305983
申请日：2014-06-16
Applicant: SK hynix memory solutions inc.
Inventor： Kwok W. Yeung , Meng-Kun Lee , Gubo Huang
CPC classification number: G06F13/1668 , G06F12/0246 , G06F13/385 , G06F2212/7207 , G06F2213/3802
Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.
Abstract translation: 第二控制器经由接口从第一控制器通信。 存储器还通过接口从第一控制器传送。 第一个控制器被配置为接口上的主控器，第二个控制器和存储器被配置为接口上的目标。
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Patent Agency Ranking
公开(公告)号：US08650453B2
公开(公告)日：2014-02-11
申请号：US13781361
申请日：2013-02-28
Applicant: SK hynix memory solutions inc.
Inventor： Kin Man Ng , Lingqi Zeng , Yu Kou , Kwok W. Yeung
IPC: H03M13/00
CPC classification number: H03M13/05 , H03M13/114
Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.
Abstract translation: 获得成本函数。 对于多个节点组中的每一个，通过为给定的节点组获得与给定的节点组相关联的一个或多个可靠性值来评估成本函数; 一个或多个可靠性值包括符号和幅度。 对于给定的节点组，选择具有最小幅度的可靠性值，其中将给定节点组的估计成本函数设置为最小量级。 至少部分地基于所评估的成本函数来选择所述多个节点组中的一个。 对所选择的节点组执行纠错解码相关处理。
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公开(公告)号：US09058290B2
公开(公告)日：2015-06-16
申请号：US14263440
申请日：2014-04-28
Applicant: SK hynix memory solutions inc.
Inventor： Ka Hou Chan , Kwok W. Yeung
CPC classification number: G06F11/1076 , G06F11/1048 , G11C2029/0411
Abstract: Accessing data at a memory is described. A request associated with a read or write operation is received, wherein the request includes a logical address associated with the memory. A physical address is generated based at least in part on the logical address. A block of data at the memory that includes data associated with the physical address is determined. Data at the determined block of data and a corresponding set of ECC from the memory are accessed. Whether the accessed data can be decoded based at least in part on the corresponding set of ECC is determined.
Abstract translation: 描述在存储器处访问数据。 接收与读取或写入操作相关联的请求，其中所述请求包括与存储器相关联的逻辑地址。 至少部分地基于逻辑地址生成物理地址。 确定包括与物理地址相关联的数据的存储器中的数据块。 访问确定的数据块的数据和来自存储器的对应的一组ECC。 确定所访问的数据是否可以至少部分地基于对应的一组ECC进行解码。
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公开(公告)号：US20140365716A1
公开(公告)日：2014-12-11
申请号：US14305983
申请日：2014-06-16
Applicant: SK hynix memory solutions inc.
Inventor： Kwok W. Yeung , Meng-Kun Lee , Gubo Huang
IPC: G06F12/02
CPC classification number: G06F13/1668 , G06F12/0246 , G06F13/385 , G06F2212/7207 , G06F2213/3802
Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.
Abstract translation: 第二控制器经由接口从第一控制器通信。 存储器还通过接口从第一控制器传送。 第一个控制器被配置为接口上的主控器，第二个控制器和存储器被配置为接口上的目标。
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公开(公告)号：US20140325313A1
公开(公告)日：2014-10-30
申请号：US14263440
申请日：2014-04-28
Applicant: SK hynix memory solutions inc.
Inventor： Ka Hou Chan , Kwok W. Yeung
IPC: G06F11/10
CPC classification number: G06F11/1076 , G06F11/1048 , G11C2029/0411
Abstract: Accessing data at a memory is described. A request associated with a read or write operation is received, wherein the request includes a logical address associated with the memory. A physical address is generated based at least in part on the logical address. A block of data at the memory that includes data associated with the physical address is determined. Data at the determined block of data and a corresponding set of ECC from the memory are accessed. Whether the accessed data can be decoded based at least in part on the corresponding set of ECC is determined.
Abstract translation: 描述在存储器处访问数据。 接收与读取或写入操作相关联的请求，其中所述请求包括与存储器相关联的逻辑地址。 至少部分地基于逻辑地址生成物理地址。 确定包括与物理地址相关联的数据的存储器中的数据块。 访问确定的数据块的数据和来自存储器的对应的一组ECC。 确定所访问的数据是否可以至少部分地基于对应的一组ECC进行解码。
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公开(公告)号：US20130246880A1
公开(公告)日：2013-09-19
申请号：US13781361
申请日：2013-02-28
Applicant: SK HYNIX MEMORY SOLUTIONS INC.
Inventor： Kin Man Ng , Lingqi Zeng , Yu Kou , Kwok W. Yeung
IPC: H03M13/05
CPC classification number: H03M13/05 , H03M13/114
Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.
Abstract translation: 获得成本函数。 对于多个节点组中的每一个，通过为给定的节点组获得与给定的节点组相关联的一个或多个可靠性值来评估成本函数; 一个或多个可靠性值包括符号和幅度。 对于给定的节点组，选择具有最小幅度的可靠性值，其中将给定节点组的估计成本函数设置为最小量级。 至少部分地基于所评估的成本函数来选择所述多个节点组中的一个。 对所选择的节点组执行纠错解码相关处理。
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