公开(公告)号：US20190251049A1

公开(公告)日：2019-08-15

申请号：US16392240

申请日：2019-04-23

Applicant: SOCIONEXT INC.

Inventor： Seiji GOTO ,  Eiichi NIMODA ,  Satoru OKAMOTO

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/36 ,  G06F13/38 ,  G06F13/42

Abstract: Processing by an information processing system is speeded up. A first semiconductor integrated circuit designates a first address of a memory connected to a second semiconductor integrated circuit that is a data transmission destination, based on first memory map information in which addresses of memories respectively used by the semiconductor integrated circuits are defined, converts the first address to a second address of the memory defined in second memory map information referred to by the data transmission destination, and outputs the second address and transmission data by using a PCIe interface. A switch transfers the second address and the transmission data to the data transmission destination by using PCIe interfaces. The data transmission destination receives the second address and the transmission data by using a PCIe interface and writes the transmission data into the reception buffer region of the memory corresponding to the second address.

公开(公告)号：US20200302069A1

公开(公告)日：2020-09-24

申请号：US16899256

申请日：2020-06-11

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Eiichi NIMODA

IPC: G06F21/60 ,  G06F9/4401 ,  G06F11/07

Abstract: In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

公开(公告)号：US20190188173A1

公开(公告)日：2019-06-20

申请号：US16273943

申请日：2019-02-12

Applicant: SOCIONEXT INC.

Inventor： Takayuki OTANI ,  Teruhiko KAMIGATA ,  Takashi KAWASAKI ,  Eiichi NIMODA

IPC: G06F13/38 ,  G06F13/16

Abstract: A bus control circuit for transferring an exclusive command between first and second bus specifications by mutually converting a first exclusive command of the first bus specification which deals with an exclusive access, and a second exclusive command of the second bus specification which doesn't deal with the exclusive access, includes an exclusive command conversion circuit receiving the first exclusive command, converting and outputting the second exclusive command, when converting from the first to second exclusive commands; an exclusive command generation circuit receiving the second exclusive command and generating the first exclusive command, when converting from the second to first exclusive commands; an exclusive response issuing circuit issuing exclusive response information for the second exclusive command, when converting from the second to first exclusive commands; and an exclusive response receiving circuit receiving exclusive response information for the second exclusive command, when converting from the first to second exclusive commands.

公开(公告)号：US20160062814A1

公开(公告)日：2016-03-03

申请号：US14936488

申请日：2015-11-09

Applicant: SOCIONEXT INC.

Inventor： Natsumi SAITO ,  Eiichi NIMODA

IPC: G06F11/07 ,  G06F1/28

CPC classification number: G06F11/079 ,  G06F1/28 ,  G06F11/0721 ,  G06F11/0745 ,  G06F11/0751 ,  G06F11/0766 ,  G06F11/30 ,  G06F11/3041 ,  G06F11/3055 ,  G06F11/3062

Abstract: In an error response circuit an analysis circuit unit analyzes a command transmitted from a first circuit section to a second circuit section, and detects a status of data transfer between the first circuit section and the second circuit section. A response circuit unit generates an error signal in accordance with the detected status of the data transfer in response to the second circuit section changing from a first power consumption state to a second power consumption state in which power consumption is lower than power consumption in the first power consumption state. A switching circuit unit transmits the error signal to the first circuit section in place of a response signal that is responsive to the command and transmitted from the second circuit section to the first circuit section.