公开(公告)号：US20140327135A1

公开(公告)日：2014-11-06

申请号：US14334229

申请日：2014-07-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Soo Won Lee ,  Kyu Won Lee ,  Eun Jin Jeong

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16112 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.

Abstract translation: 半导体器件具有基板。 导电层形成在衬底上。 引线板上的双面电镀凸块形成在衬底上。 在导电层和基板上形成绝缘层。 使用激光直接烧蚀工艺去除铅焊盘上的双面电镀凸块上绝缘层的一部分。 绝缘层是层叠层。 导线焊盘上的双面电镀凸块在导线焊盘上有一个很大的凹凸。 半导体管芯安装在衬底上。 半导体管芯具有复合导电互连结构。 半导体管芯具有第一凸块和在第一凸块和第二凸块之间具有从90-150微米的间距的第二凸块。 双面电镀接触焊盘形成在与双面电镀凸块焊盘相对的基板的表面上。

公开(公告)号：US09799621B2

公开(公告)日：2017-10-24

申请号：US14334229

申请日：2014-07-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Soo Won Lee ,  Kyu Won Lee ,  Eun Jin Jeong

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16112 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.