公开(公告)号：US08729687B2

公开(公告)日：2014-05-20

申请号：US13649834

申请日：2012-10-11

Applicant: STATS ChipPAC Ltd.

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/31 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成第一外部互连; 在第一外部互连下方安装第一集成电路管芯; 在第一集成电路管芯上以不在第一外部互连上的偏移配置堆叠第二集成电路管芯; 将所述第一集成电路管芯与所述第一外部互连件连接; 并且将所述第二集成电路管芯与所述第一外部互连件封装，并且所述第一集成电路管芯部分地露出。

公开(公告)号：US20150001741A1

公开(公告)日：2015-01-01

申请号：US13929426

申请日：2013-06-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Koo Hong Lee ,  Tae Keun Lee

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49833 ,  H01L23/13 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/15331 ,  H01L2924/00

Abstract: A semiconductor device includes a first substrate. The first substrate may be a wafer-level interposer or a die-level interposer. A portion of the first substrate is removed to form a beveled edge. The beveled edge may be formed during singulation of the first substrate. A second substrate is disposed over the first substrate. The beveled edge is oriented towards the second substrate. A semiconductor die is disposed over the second substrate. The first and second substrates are disposed within a cavity of a mold. An encapsulant is deposited within the cavity over a first surface of the first substrate between the first and second substrates. The beveled edge reduces encapsulant flow onto a second surface of the first substrate opposite the first surface. The second surface of the first substrate remains free from the encapsulant. The first substrate is singulated before or after the encapsulant is deposited.

Abstract translation: 半导体器件包括第一衬底。 第一衬底可以是晶片级插入器或晶片级插入器。 去除第一衬底的一部分以形成斜边。 斜切边缘可以在第一基板的分割期间形成。 第二基板设置在第一基板上。 斜边缘朝向第二基板。 半导体管芯设置在第二衬底上。 第一和第二基板设置在模具的空腔内。 密封剂在第一和第二基底之间的第一基底的第一表面上沉积在空腔内。 倾斜的边缘减少了密封剂流到与第一表面相对的第一基底的第二表面上。 第一衬底的第二表面保持不含密封剂。 第一衬底在密封剂沉积之前或之后被分离。