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公开(公告)号:US20180294233A1
公开(公告)日:2018-10-11
申请号:US15485085
申请日:2017-04-11
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: InSang Yoon , SeungYong Chai , SoYeon Park
IPC: H01L23/552 , H01L23/00 , H01L23/498 , H01L23/31 , H01L21/48 , H01L21/56
CPC classification number: H01L23/552 , H01L21/485 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L23/3114 , H01L23/49822 , H01L23/49838 , H01L24/81 , H01L24/97 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/81815 , H01L2224/97 , H01L2924/014 , H01L2224/81
Abstract: A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.
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公开(公告)号:US10319684B2
公开(公告)日:2019-06-11
申请号:US15485085
申请日:2017-04-11
Applicant: STATS ChipPAC Pte. Ltd.
Inventor: InSang Yoon , SeungYong Chai , SoYeon Park
IPC: H01L21/48 , H01L21/56 , H01L21/78 , H01L23/00 , H01L23/31 , H01L21/768 , H01L23/498 , H01L23/538 , H01L23/552
Abstract: A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.
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