公开(公告)号：US10903304B2

公开(公告)日：2021-01-26

申请号：US15460690

申请日：2017-03-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Meenakshi Padmanathan ,  Seung Wook Yoon ,  YongTaek Lee

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L49/02 ,  H01L23/532 ,  H01L23/66

Abstract: A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties.

公开(公告)号：US20170186690A1

公开(公告)日：2017-06-29

申请号：US15460690

申请日：2017-03-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Meenakshi Padmanathan ,  Seung Wook Yoon ,  YongTaek Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L49/02 ,  H01L23/528

CPC classification number: H01L28/10 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/66 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties.

公开(公告)号：US20240404956A1

公开(公告)日：2024-12-05

申请号：US18325805

申请日：2023-05-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongTaek Lee ,  JaeMyeong Kim ,  DaAe Lee

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/66

Abstract: A semiconductor device has a first substrate. A first semiconductor die and second semiconductor die are disposed over the substrate. An interconnect bridge is disposed over the first semiconductor die and second semiconductor die. The interconnect bridge has a second substrate. A conductive trace is formed over the second substrate. The conductive trace is electrically coupled from the first semiconductor die to the second semiconductor die. An IPD is also formed over the second substrate. The IPD is electrically coupled between the first semiconductor die and second semiconductor die. An encapsulant is deposited over the first substrate, first semiconductor die, second semiconductor die, and interconnect bridge.

公开(公告)号：US20240047386A1

公开(公告)日：2024-02-08

申请号：US17817089

申请日：2022-08-03

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongTaek Lee ,  OhYoung Kwon ,  SeungMan Hong

IPC: H01L23/64 ,  H01L23/00 ,  H01L21/822

CPC classification number: H01L23/647 ,  H01L24/48 ,  H01L24/16 ,  H01L24/73 ,  H01L21/822 ,  H01L2224/48227 ,  H01L2224/16227 ,  H01L2224/73257 ,  H01L28/10

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. The semiconductor wafer has a low resistivity. An insulating layer is formed over the semiconductor wafer. A first IPD is formed over the insulating layer. The first IPD can be a capacitor, resistor, or inductor. A second IPD is formed over a second surface of the semiconductor wafer opposite the first surface of the semiconductor wafer. An interconnect structure is formed over the first IPD. An interconnect substrate is provided with the semiconductor die disposed over the interconnect substrate. A bond wire is formed between the interconnect structure and the interconnect substrate. Alternatively, an active device is formed in a second surface of the semiconductor die opposite the first surface of the semiconductor die. The semiconductor die incorporates the hybrid substrate to allow IPD and active devices to be formed from a single substrate.