REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
    1.
    发明申请
    REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM 有权
    减少复杂非二进制LDPC解码算法

    公开(公告)号:US20130212451A1

    公开(公告)日:2013-08-15

    申请号:US13764649

    申请日:2013-02-11

    Applicant: STEC, Inc.

    Abstract: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

    Abstract translation: 引入定制解码算法,结合相应的解码结构,以解决已知解码器的许多复杂性和大的存储器要求。 一个系统。 变量节点形成四个分量的置信向量,一个分量用于存储器单元的每个状态,并将当前主要分量(例如,最大的)传递到一个或多个校验节点。 校验节点基于从变量节点接收到的所有组件计算临时组件和相应的索引,它们传回给相应的变量节点。 变量节点基于从相应校验节点接收到的临时节点更新置信向量,并且基于置信度向量中的哪个组件当前是主要组件来确定对应的存储器单元的正确状态。

    WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
    2.
    发明申请
    WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM 有权
    FLASH系统中的WORD-LINE INTER-CELL INTERFERENCE检测器

    公开(公告)号:US20130163327A1

    公开(公告)日:2013-06-27

    申请号:US13725689

    申请日:2012-12-21

    Applicant: STEC, Inc.

    CPC classification number: G11C16/3431 G11C11/5642 G11C2211/5634

    Abstract: Aspects of the subject technology encompass a method for retrieving information stored in flash memory. In certain implementations, the method can include operations for reading a plurality of memory cells in a word line, generating a plurality of read signals based on the reading of the plurality of memory cells and identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in the word line. In certain aspects, the method can further include operations for generating an output for the first memory cell, wherein the output is based on the first and second read signals. A data storage system and article of manufacture are also provided.

    Abstract translation: 主题技术的方面包括用于检索存储在闪速存储器中的信息的方法。 在某些实现中,该方法可以包括用于读取字线中的多个存储器单元的操作,基于多个存储器单元的读取产生多个读取信号,并从多个读取信号中识别出第一个 与第一存储器单元相关联的读取信号和与第二存储器单元相关联的第二读取信号,其中第一存储器单元与字线中的第二存储器单元相邻。 在某些方面,该方法还可以包括用于产生第一存储器单元的输出的操作,其中输出基于第一和第二读取信号。 还提供了数据存储系统和制品。

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