公开(公告)号：US20150221648A1

公开(公告)日：2015-08-06

申请号：US14169875

申请日：2014-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Jocelyne Gimbert

IPC: H01L27/092 ,  H01L21/70 ,  H01L21/265 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/707 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract translation: 描述了形成在绝缘体上半导体衬底中的晶体管形成高掺杂的超薄层的方法和结构。 可以在超薄半导体层中实现高掺杂浓度以改善器件特性。 在升高的温度下进行离子注入可以缓解高达约30％的化学计量掺杂浓度的缺陷形成。 面内应力源可以形成在与超薄半导体层中形成的晶体管相邻的位置。

公开(公告)号：US10134898B2

公开(公告)日：2018-11-20

申请号：US14982052

申请日：2015-12-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Jocelyne Gimbert

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L29/165

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

公开(公告)号：US09876110B2

公开(公告)日：2018-01-23

申请号：US14169875

申请日：2014-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Jocelyne Gimbert

IPC: H01L27/12 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/70 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/707 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

公开(公告)号：US11699757B2

公开(公告)日：2023-07-11

申请号：US16168771

申请日：2018-10-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Jocelyne Gimbert

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/70 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/707 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/1608 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/165 ,  H01L29/66795

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

公开(公告)号：US20190058062A1

公开(公告)日：2019-02-21

申请号：US16168771

申请日：2018-10-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Jocelyne Gimbert

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/66

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.