公开(公告)号：US20220271740A1

公开(公告)日：2022-08-25

申请号：US17676005

申请日：2022-02-18

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco VITI

IPC: H03K3/027 ,  H03K19/20

Abstract: A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.

公开(公告)号：US20240081778A1

公开(公告)日：2024-03-14

申请号：US17943643

申请日：2022-09-13

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano PASSI ,  Marco VITI

IPC: A61B8/00 ,  A61B8/08 ,  G01S7/52 ,  G01S15/89

CPC classification number: A61B8/4494 ,  A61B8/5207 ,  A61B8/5292 ,  A61B8/54 ,  G01S7/5202 ,  G01S15/8915

Abstract: A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.

公开(公告)号：US20240072775A1

公开(公告)日：2024-02-29

申请号：US18466562

申请日：2023-09-13

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco VITI

IPC: H03K3/027 ,  H03K19/20

CPC classification number: H03K3/027 ,  H03K19/20

Abstract: A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.