公开(公告)号：US20230244413A1

公开(公告)日：2023-08-03

申请号：US17810093

申请日：2022-06-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0679

Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.

公开(公告)号：US20240045815A1

公开(公告)日：2024-02-08

申请号：US18365031

申请日：2023-08-03

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/1045

CPC classification number: G06F13/1668 ,  G06F13/4063 ,  G06F12/1063

Abstract: A FLASH memory device includes a FLASH memory having an array of non-volatile memory cells and a volatile memory. A FLASH memory interface is arranged outside of the FLASH memory, and a first communication bus couples the FLASH memory interface to the array of memory cells. A second communication bus couples the FLASH memory interface to the volatile memory.

公开(公告)号：US12008244B2

公开(公告)日：2024-06-11

申请号：US17810093

申请日：2022-06-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.

公开(公告)号：US20230385149A1

公开(公告)日：2023-11-30

申请号：US18313686

申请日：2023-05-08

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F11/10 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F12/0246 ,  G06F13/1668

Abstract: In accordance with an embodiment, a method includes: performing a first write operation comprising writing a first data packet to a first portion of a first line of a flash memory; and performing a second write operation comprising writing a second data packet to a second portion of the first line of the flash memory, wherein the first line comprises the first data packet and the second data packet after performing the first write operation and the second write operation.

公开(公告)号：US11853241B2

公开(公告)日：2023-12-26

申请号：US18065475

申请日：2022-12-13

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi ,  Sylvain Meyer

IPC: G06F13/24 ,  G06F13/16 ,  G06F21/85 ,  H03K19/20 ,  G06F1/3237

CPC classification number: G06F13/24 ,  G06F1/3237 ,  G06F13/1689 ,  G06F21/85 ,  H03K19/20

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

公开(公告)号：US20230384953A1

公开(公告)日：2023-11-30

申请号：US18318416

申请日：2023-05-16

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.

公开(公告)号：US11550744B2

公开(公告)日：2023-01-10

申请号：US17229307

申请日：2021-04-13

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Jawad Benhammadi ,  Sylvain Meyer

IPC: G06F13/24 ,  G06F13/16 ,  G06F21/85 ,  H03K19/20 ,  G06F1/3237

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

公开(公告)号：US12271607B2

公开(公告)日：2025-04-08

申请号：US18318416

申请日：2023-05-16

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F3/06

Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.

公开(公告)号：US20230113667A1

公开(公告)日：2023-04-13

申请号：US18065475

申请日：2022-12-13

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi ,  Sylvain Meyer

IPC: G06F13/24 ,  G06F13/16 ,  G06F21/85 ,  H03K19/20 ,  G06F1/3237

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

公开(公告)号：US20210318972A1

公开(公告)日：2021-10-14

申请号：US17229307

申请日：2021-04-13

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Jawad Benhammadi ,  Sylvain Meyer

IPC: G06F13/24 ,  H03K19/20 ,  G06F13/16 ,  G06F21/85

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.