公开(公告)号：US20140122837A1

公开(公告)日：2014-05-01

申请号：US14064936

申请日：2013-10-28

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Peng Fei Zhu ,  Hong-Xia Sun ,  Yong Qiang Wu

IPC: G06F9/30

CPC classification number: G06F9/3012 ,  G06F9/384

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract translation: 提供了利用多库实现物理寄存器映射表的处理器架构的实施例。 将结构寄存器与物理寄存器相关联的寄存器重命名系统包括物理寄存器映射表和重命名逻辑。 物理寄存器映射表具有多个表示每个物理寄存器的状态的条目。 映射表具有多个非重叠部分，每个部分具有映射表的相应条目。 重命名逻辑被耦合以并行地搜索映射表的多个部分以识别指示相应物理寄存器具有第一状态的条目。 重命名逻辑选择性地将多个体系结构寄存器中的每一个相关于被识别为处于第一状态的相应物理寄存器。 还提供了利用多库实现物理寄存器映射表的方法。