公开(公告)号：US09164903B2

公开(公告)日：2015-10-20

申请号：US13650503

申请日：2012-10-12

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Davide Sarta

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F12/06 ,  G06F12/0607

Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.

Abstract translation: 一种包括多个输出的存储器管理装置，每个输出被配置为与多个存储器中的相应一个存储器接口; 以及控制器，其被配置为使得分配给所述存储器的每个缓冲器在所述多个存储器中的每一个之间基本上相等地被划分。

公开(公告)号：US20130097401A1

公开(公告)日：2013-04-18

申请号：US13650503

申请日：2012-10-12

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Davide Sarta

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F12/06 ,  G06F12/0607

Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.

Abstract translation: 一种包括多个输出的存储器管理装置，每个输出被配置为与多个存储器中的相应的一个存储器接口; 以及控制器，其被配置为使得分配给所述存储器的每个缓冲器在所述多个存储器中的每一个之间基本上相等地被划分。