公开(公告)号：US20240304731A1

公开(公告)日：2024-09-12

申请号：US18594210

申请日：2024-03-04

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET ,  Marc BATTISTA

IPC: H01L29/8605 ,  H01L27/06

CPC classification number: H01L29/8605 ,  H01L27/0629

Abstract: An electronic device includes first and second diffused resistors in contact with each other to form a PN junction. The device is configured so that a potential difference between the first and second resistors is constant at any point of the PN junction. The PN junction is reverse-biased.

公开(公告)号：US20250117353A1

公开(公告)日：2025-04-10

申请号：US18483286

申请日：2023-10-09

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET ,  Gilles DIONIS

IPC: G06F13/42 ,  G06F13/38

Abstract: A synchronous serial communication controller, a synchronous serial communication peripheral component, and a computer-implemented method enabling synchronous serial communication between the synchronous serial communication controller and the synchronous serial communication peripheral component are provided. The example synchronous serial communication controller includes a serial communication interface, configured with a clock logic wire, a data output logic wire, a data input logic wire, and a shared select line logic wire. The shared select line logic wire is electrically connected to a plurality of peripheral components. A selected peripheral component of the plurality of peripheral components is indicated by chip identification data transmitted on the data output logic wire.

公开(公告)号：US20250119065A1

公开(公告)日：2025-04-10

申请号：US18481333

申请日：2023-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET ,  Guglielmo SIRNA

IPC: H02M7/219 ,  H02J50/10

Abstract: A bridge rectifier circuit and a wireless power receiver configured to receive high voltage AC inputs and generate a stable DC voltage without exposing the bridge rectifier circuitry components to damaging high voltages are provided. The example bridge rectifier includes a plurality of rectifying transistors positioned to generate a DC voltage upon receiving an AC current. The example bridge rectifier circuitry further includes voltage control circuitry designed to output an intermediate voltage to a terminal of one or all of the rectifying transistors of the bridge rectifier. The output intermediate voltage prevents a voltage difference across the terminal of the rectifying transistor from exceeding a maximum voltage rating of the rectifying transistor.

公开(公告)号：US20240170960A1

公开(公告)日：2024-05-23

申请号：US18512292

申请日：2023-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.

公开(公告)号：US20240410932A1

公开(公告)日：2024-12-12

申请号：US18206192

申请日：2023-06-06

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET

IPC: G01R31/26 ,  G01R19/165

Abstract: Disclosed herein is a detector circuit including a first detector configured to receive an input signal and generate a first detector output signal indicative of the input signal having reached a first activation threshold and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicative of the input signal having reached a second activation threshold. A logic circuit is configured to perform a logical operation on the first and second detector output signals to generate an output indicative of the input signal having reached a voltage equal to the second activation threshold.