公开(公告)号：US20250111875A1

公开(公告)日：2025-04-03

申请号：US18815356

申请日：2024-08-26

Applicant: STMicroelectronics International N.V.

Inventor： Sant Swaroop SHRIVASTAVA ,  Hitesh CHAWLA ,  Mohd Javed IKHLAS ,  Sachin GULYANI

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: A memory system includes a memory array with first dummy read cells that discharge a dummy bit line, each of the first dummy read cells including a transistor coupled between the dummy bit line and a first ground node that is connected to a ground reference. Second dummy read cells discharge the dummy bit line, each of the dummy read cells including a transistor coupled between the dummy bit line and a second ground node. The dummy read cells cooperate to discharge the dummy bit line in a dummy read operation to provide a self-timing signal. Read circuitry retrieves data from a selected row in the memory array during a read operation, in response to the self-timing signal. Ground generation circuitry connects the second ground node to the ground reference or allows the second ground to float, based upon a control signal.

公开(公告)号：US20250069678A1

公开(公告)日：2025-02-27

申请号：US18939751

申请日：2024-11-07

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20240143239A1

公开(公告)日：2024-05-02

申请号：US18379373

申请日：2023-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Manuj AYODHYAWASI ,  Nitin CHAWLA

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0655

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

公开(公告)号：US20240112748A1

公开(公告)日：2024-04-04

申请号：US18228118

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Tanuj KUMAR ,  Hitesh CHAWLA ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G11C29/12015 ,  G11C29/32 ,  G11C2029/1204

Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.

公开(公告)号：US20240071546A1

公开(公告)日：2024-02-29

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

CPC classification number: G11C29/1201 ,  G11C29/36 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/3602

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20240069096A1

公开(公告)日：2024-02-29

申请号：US18228048

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G01R31/317 ,  G11C11/418 ,  G11C11/419

CPC classification number: G01R31/31724 ,  G11C11/418 ,  G11C11/419

Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.