公开(公告)号：US12299444B2

公开(公告)日：2025-05-13

申请号：US18323049

申请日：2023-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Sofiane Landi

IPC: G06F9/30 ,  G06F9/345

Abstract: A system includes a memory and a processor coupled to the memory. The processor executes an instruction set having a word size. The processor includes arithmetic processing circuitry, which, in operation, executes arithmetic operations on operands having the word size. The arithmetic processing circuitry includes an arithmetic logic circuit (ALU) having an operand size smaller than the word size of the instruction set. The ALU, in operation, generates partial results of the arithmetic operations. A multiplexing network coupled to inputs of the ALU provides portions of the operands to the ALU. A shift register having the word size of the instruction set accumulates partial results generated by the ALU over a plurality of clock cycles and outputs results of the arithmetic operations based on the accumulated partial results.