公开(公告)号：US20230230650A1

公开(公告)日：2023-07-20

申请号：US17580458

申请日：2022-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Gabriele Solcia

IPC: G11C29/36 ,  G11C29/46 ,  G11C29/12 ,  G11C7/10 ,  H03K19/173 ,  H03K19/20

CPC classification number: G11C29/36 ,  G11C7/1036 ,  G11C29/46 ,  G11C29/1201 ,  H03K19/20 ,  H03K19/1737 ,  G11C2029/3602

Abstract: A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.

公开(公告)号：US11984178B2

公开(公告)日：2024-05-14

申请号：US17580458

申请日：2022-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Gabriele Solcia

IPC: G11C29/36 ,  G11C7/10 ,  G11C29/12 ,  G11C29/46 ,  H03K19/173 ,  H03K19/20

CPC classification number: G11C29/36 ,  G11C7/1036 ,  G11C29/1201 ,  G11C29/46 ,  H03K19/1737 ,  H03K19/20 ,  G11C2029/3602

Abstract: A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.