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公开(公告)号：US09893689B2
公开(公告)日：2018-02-13
申请号：US15192863
申请日：2016-06-24
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Riccardo Zurla , Alessandro Cabrini , Guido Torelli
CPC classification number: H03F1/14 , H03F1/083 , H03F1/086 , H03F3/45 , H03F3/45174 , H03F3/45183 , H03F3/45475 , H03F2200/375 , H03F2203/45138 , H03F2203/45222
Abstract: According to an embodiment, an operational amplifier includes a first amplifier stage coupled between an input node and an intermediate node, a second amplifier stage coupled between the intermediate node and an output node, a compensation capacitor having a first terminal coupled to the intermediate node and a second terminal, and a compensation amplifier coupled between the output node and the second terminal. The compensation amplifier has a positive gain greater than one.
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公开(公告)号：US11189343B2
公开(公告)日：2021-11-30
申请号：US16940837
申请日：2020-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Laura Capecchi , Marco Pasotti , Marcella Carissimi , Riccardo Zurla
Abstract: A current-generator circuit includes an output-current generator circuit having a control branch to be coupled to a control current generator and adapted to provide a control current pulse and a driver electrically coupled between the control branch and the output leg. A compensation circuit includes a first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse and a second compensation branch coupled in a current mirror configuration with the first compensation branch to receive the compensation current pulse. The second compensation branch includes a resistive block having an electrical resistance that is a function of a resistance of an output load. The second compensation branch is electrically coupled to the control branch and the driver is electrically coupled to the control branch and to the output leg.
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公开(公告)号：US09921598B1
公开(公告)日：2018-03-20
申请号：US15397137
申请日：2017-01-03
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla
CPC classification number: G05F3/26
Abstract: A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to supply voltage node. The gates of the input and output transistor are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at a mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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公开(公告)号：US12046987B2
公开(公告)日：2024-07-23
申请号：US17582431
申请日：2022-01-24
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla , Marcella Carissimi
CPC classification number: H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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Patent Agency Ranking
公开(公告)号：US10978146B2
公开(公告)日：2021-04-13
申请号：US16662911
申请日：2019-10-24
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Riccardo Zurla , Alessandro Cabrini , Guido Torelli , Flavio Giovanni Volpe
Abstract: A phase-change memory device, comprising: a memory array of PCM cells, a variable current generator, and a sense amplifier. The current generator comprises a reference array of PCM cells programmed in SET resistance state. The phase-change memory device further comprises a decoder for addressing each cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; and a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current to be lower than said mean value.
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公开(公告)号：US20210035637A1
公开(公告)日：2021-02-04
申请号：US16940837
申请日：2020-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Laura Capecchi , Marco Pasotti , Marcella Carissimi , Riccardo Zurla
Abstract: A current-generator circuit includes an output-current generator circuit having a control branch to be coupled to a control current generator and adapted to provide a control current pulse and a driver electrically coupled between the control branch and the output leg. A compensation circuit includes a first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse and a second compensation branch coupled in a current mirror configuration with the first compensation branch to receive the compensation current pulse. The second compensation branch includes a resistive block having an electrical resistance that is a function of a resistance of an output load. The second compensation branch is electrically coupled to the control branch and the driver is electrically coupled to the control branch and to the output leg.
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公开(公告)号：US20240339917A1
公开(公告)日：2024-10-10
申请号：US18746752
申请日：2024-06-18
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla , Marcella Carissimi
CPC classification number: H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US10139850B2
公开(公告)日：2018-11-27
申请号：US15887323
申请日：2018-02-02
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla
Abstract: A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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公开(公告)号：US20180188763A1
公开(公告)日：2018-07-05
申请号：US15887323
申请日：2018-02-02
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla
IPC: G05F3/26
CPC classification number: G05F3/26
Abstract: A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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