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    Memory unit
    2.
    发明授权
    Memory unit 失效
    记忆单元

    公开(公告)号：US3560941A

    公开(公告)日：1971-02-02

    申请号：US3560941D

    申请日：1967-08-29

    Applicant: SUSQUEHANNA CORP

    Inventor： WALLACE JACOB L JR

    IPC: G11C27/02 ,  H03M1/00 ,  H04M1/2745 ,  G11C17/00

    CPC classification number: G11C27/02 ,  H03M1/50 ,  H04M1/274591

    Abstract: AN EMBODIMENT OF THE PRESENT INVENTION SHOWS A CIRCUIT BOARD USED IN THE MEMORY OF A REPERTORY DIALER. THE BOARD HS TEN COLUMNS OF ELECTRICALLY-CONNECTED SOCKETS, EACH COLUMN BEING HEADED BY A RESISTOR WEIGHTED IN VALUE ACCORDING TO THE COLUMN IN WHICH IT IS LOCATED. EACH COLUMN CORRESPONDS TO A DIGIT VALUE IN AN ADDRESS. TEN ROWS, HAVING A SOCKET IN EACH ROW, ARE ALSO PROVIDED AND CORRESPOND TO THE DIGIT POSITIONS IN AN ADDRESS. TO PROGRAM THE CIRCUIT BOARD, WIRE LEAD IS CONNECTED FROM THE SOCKET IN EACH ROW TO A SOCKET IN THE COLUMN CORRESPONDING TO THE DIGIT VALUE. THIS BOARD THEREFORE PERMITS THE PROGRAMMING OF INFORMATION DIRECTLY IN ANALOG FORM. THE MEMORY, COMPRISING A PLURALITY OF BOARDS, STORES THREE-DIMENSIONAL INFORMATION IN A TWO-DIMENSIONAL MATRIX. THE WEIGHTED RESISTORS PROVIDE THE THIRD-DIMENSIONAL INFORMATION.

    Duplex control circuit
    3.
    发明授权
    Duplex control circuit 失效
    双重控制电路

    公开(公告)号：US3581006A

    公开(公告)日：1971-05-25

    申请号：US3581006D

    申请日：1968-03-22

    Applicant: SUSQUEHANNA CORP

    Inventor： WALLACE JACOB L JR

    IPC: H04L5/14 ,  H04L25/04

    CPC classification number: H04L5/1461

    Abstract: An example of the duplex control circuit is a circuit formed of two logic flip-flops connected between two channels of a halfduplex telegraph circuit. This duplex control circuit functions to prevent reflections or feedback of the transmissions into the inactive channel. Each channel is controlled by one of the flipflops whereby the flip-flop controlling the inactive channel is set and locks this channel to a marking condition whenever a spacing signal is processed by the active channel and does not become reset until this spacing signal terminates at the input to the inactive channel.

    Method and apparatus for measuring speed-error in a pulse train
    6.
    发明授权
    Method and apparatus for measuring speed-error in a pulse train 失效
    用于测量脉冲火车速度误差的方法和装置

    公开(公告)号：US3699255A

    公开(公告)日：1972-10-17

    申请号：US3699255D

    申请日：1970-06-24

    Applicant: SUSQUEHANNA CORP

    Inventor： WALLACE JACOB L JR

    IPC: H04L12/26 ,  H04L25/04 ,  H04L25/02

    CPC classification number: H04L1/248

    Abstract: A measurement of transmission speed-error can be obtained by utilizing the present inventive concepts with conventional pulse or telegraph distortion measuring apparatus. For each character in the pulse train fed to the apparatus, a period of time is established for making measurements. The transitions which occur during this time period are measured in the normal manner and displayed. The meter or other display apparatus is designed to divide the reading by an appropriate number in order to compensate for the cumulative effect of speed error, and an indication is also made as to whether the speed is faster or slower than normal.

    Abstract translation: 通过利用本发明的概念与传统的脉冲或电报失真测量装置可以获得传输速度误差的测量值。 对于馈送到设备的脉冲串中的每个字符，建立用于进行测量的一段时间。 在该时间段期间发生的转变以正常方式测量并显示。 仪表或其他显示装置被设计为将读数除以适当的数字，以补偿速度误差的累积效应，并且还指示速度是否比正常速度更快或更慢。

    Interlocking switch arrangement
    7.
    发明授权
    Interlocking switch arrangement 失效
    互锁开关装置

    公开(公告)号：US3597737A

    公开(公告)日：1971-08-03

    申请号：US3597737D

    申请日：1968-06-21

    Applicant: SUSQUEHANNA CORP

    Inventor： WALLACE JACOB L JR ,  BROWN ROBERT M

    IPC: H04Q3/00 ,  H04Q1/00 ,  H04M3/00

    CPC classification number: H04Q3/0012

    Abstract: An example of an interlocking switch arrangement is a matrix design having an interlocking circuit connected at each matrix cross point. Each interlocking circuit has a relay which when actuated closes the matrix at its associated cross point. Prior to actuation of its relay, this circuit grounds the matrix column and row buses at its cross point. This serves to open the matrix at any other cross point in the same row and column thereby preventing the matrix from being connected at more than one cross point in any column or row at the same time. The matrix design affords versatility in that it permits interlocking circuits to be easily added to or removed from the matrix without affecting or requiring any altering of the other interlocking circuits.

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