DC-DC CONVERTER OUTPUT REGULATION SYSTEMS AND METHODS

    公开(公告)号:US20220173659A1

    公开(公告)日:2022-06-02

    申请号:US17109087

    申请日:2020-12-01

    Abstract: A circuit includes a controller circuit configured to receive an output voltage of a converter and adjust a switching frequency of the converter in response to a status of an output load and an output load sensing circuit configured to determine the status of the output load and provide the peak current to the controller circuit. The output load sensing circuit may include a first timer configured to provide a delayed first signal to a peak current control in response to the output load being a heavy load. A second timer may be configured to provide a delayed second signal to the peak current control in response to the output load being a light load. The peak current control may be configured to adjust a peak current based on the received first signal and the second signal and configured to provide the peak current to the controller circuit.

    CLASS-G CONTROL SYSTEM WITH LOW LATENCY SIGNAL PATH

    公开(公告)号:US20210184638A1

    公开(公告)日:2021-06-17

    申请号:US17118411

    申请日:2020-12-10

    Abstract: Systems and methods include a digital control module that receives and processes audio data for output through a loudspeaker. An analog block receives the audio data and the power control signal and amplifies the audio data for output. A first processing path includes a buffer to delay the audio data, a first component to combine the buffered audio data and anti-noise. A second processing path includes an absolute value block to receive the audio data and an envelope detector to receive the absolute value data and generate a maximum value for the envelope. An anti-noise path includes an absolute value block configured to determine an anti-noise absolute value which is combined with the absolute value anti-noise data. A power generator receives the output from the envelope detector and updates a power level to approximate a minimum powered needed to process the audio signal.

    ACTIVE COMMON MODE COMPENSATION FOR IMPROVED AMPLIFIER PERFORMANCE

    公开(公告)号:US20220311393A1

    公开(公告)日:2022-09-29

    申请号:US17213084

    申请日:2021-03-25

    Abstract: Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

    LOW DELAY, LOW POWER AND HIGH LINEARITY CLASS-D MODULATION LOOP

    公开(公告)号:US20210203286A1

    公开(公告)日:2021-07-01

    申请号:US17119978

    申请日:2020-12-11

    Abstract: Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

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