公开(公告)号：US20200382104A1

公开(公告)日：2020-12-03

申请号：US16425813

申请日：2019-05-29

Applicant: SYNAPTICS INCORPORATED

Inventor： Jacky Li ,  Jens Kristian Poulsen ,  Hari Hariharan

IPC: H03H17/04 ,  H03H17/06

Abstract: Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.

公开(公告)号：US10848131B1

公开(公告)日：2020-11-24

申请号：US16425813

申请日：2019-05-29

Applicant: SYNAPTICS INCORPORATED

Inventor： Jacky Li ,  Jens Kristian Poulsen ,  Hari Hariharan

IPC: H03H17/04 ,  H03H17/06

Abstract: Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.