Low delay, low power and high linearity class-D modulation loop

    公开(公告)号:US11368132B2

    公开(公告)日:2022-06-21

    申请号:US17119978

    申请日:2020-12-11

    Abstract: Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

    Active common mode compensation for improved amplifier performance

    公开(公告)号:US11522507B2

    公开(公告)日:2022-12-06

    申请号:US17213084

    申请日:2021-03-25

    Abstract: Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

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