公开(公告)号：US20250124866A1

公开(公告)日：2025-04-17

申请号：US18759934

申请日：2024-06-30

Applicant: Samsung Display Co., LTD.

Inventor： Sung Yoon HWANG ,  Gi Chang LEE ,  Sang Yong NO ,  Kyung Ho KIM

IPC: G09G3/3233

Abstract: A sub-pixel includes a fourth transistor including a first electrode connected to the third node, a second electrode connected to a second power line, to which a reference voltage is applied, and a gate electrode connected to a first emission control line; a fifth transistor including a first electrode connected to the first node, a second electrode connected to a fourth node, and a gate electrode connected to a second emission control line; a capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light emitting element including a first electrode connected to the fourth node and a second electrode connected to a fourth power line, to which a second driving voltage is applied.

公开(公告)号：US20250148978A1

公开(公告)日：2025-05-08

申请号：US18775875

申请日：2024-07-17

Applicant: Samsung Display Co., LTD.

Inventor： Kyung Ho KIM ,  Gi Chang LEE ,  Sung Yoon HWANG

IPC: G09G3/3233 ,  G09G3/20 ,  G09G3/3266

Abstract: A display device includes: pixels connected to scan lines and emission control lines; a scan driver to supply a scan signal to the scan lines according to scan clock signals; a first emission driver to supply a first emission control signal to the emission control lines according to emission clock signals, when the display device is driven in a first mode; a second emission driver to supply a second emission control signal to the emission control lines according to the scan signal, when the display device is driven in a second mode; and a timing controller to control the scan driver, the first emission driver, and the second emission driver.

公开(公告)号：US20250124845A1

公开(公告)日：2025-04-17

申请号：US18819235

申请日：2024-08-29

Applicant: Samsung Display Co., LTD.

Inventor： Kyung Ho KIM ,  Gi Chang LEE ,  Sung Yoon HWANG

IPC: G09G3/20

Abstract: A clock selection circuit includes: a control circuit to output a first control signal and a second control signal, when at least one scan signal of a previous stage scan signal or a next stage scan signal is input; and a selection circuit to receive clock signals, and output the clock signals when the first control signal and the second control signal are input.

公开(公告)号：US20250123652A1

公开(公告)日：2025-04-17

申请号：US18908204

申请日：2024-10-07

Applicant: Samsung Display Co., LTD.

Inventor： Kyung Ho KIM ,  Sang Yong NO ,  Sung Yoon HWANG

IPC: G06F1/08

Abstract: According to one or more embodiments of the present disclosure, a clock selection circuit includes an inverter configured to receive an input signal through a first input terminal, and at least one controller configured to receive at least one clock signal and configured to output the clock signal when the input signal is supplied to the inverter.