公开(公告)号：US20200381311A1

公开(公告)日：2020-12-03

申请号：US16707118

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung Kim ,  Chanhyeong Lee ,  Jinkyu Jang ,  Rakhwan Kim ,  Dongsoo Lee

IPC: H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor device may include a channel pattern stacked on a substrate and a gate electrode on the substrate. The channel pattern includes semiconductor patterns. The gate electrode extends to cross the channel pattern. The gate electrode may include dielectric layers, first work function adjusting patterns, and second work function adjusting patterns. The dielectric layers may enclose the semiconductor patterns, respectively. The first work function adjusting patterns may enclose the dielectric layers, respectively, and the second work function adjusting patterns may enclose the first work function adjusting patterns, respectively. The first work function adjusting patterns may be formed of an aluminum-containing material, and each corresponding one of the first work function adjusting patterns may be in contact with a corresponding one of the second work function adjusting patterns enclosing the corresponding one of the first work function adjusting patterns.

公开(公告)号：US12100736B2

公开(公告)日：2024-09-24

申请号：US17513262

申请日：2021-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanhyeong Lee ,  Sangyong Kim ,  Jaejung Kim ,  Byounghoon Lee

IPC: H01L29/10 ,  H01L29/08

CPC classification number: H01L29/1033 ,  H01L29/0847

Abstract: A semiconductor device includes a first active region on a substrate, channel layers disposed on the first active region to be spaced apart from each other in a vertical direction, a first gate structure disposed on the first active region and surrounding each channel layer, and a first source/drain region on the first active region on at least one side of the first gate structure. The channel layers include first to third channel layers. The first gate structure includes a first gate electrode and a first gate dielectric layer. The first gate dielectric layer includes first to third portions surrounding the first to third channel layers, respectively. The second portion has a thickness greater than a thickness of the first portion, and the third portion has a thickness greater than the thickness of the second portion.

公开(公告)号：US20220238653A1

公开(公告)日：2022-07-28

申请号：US17513262

申请日：2021-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanhyeong Lee ,  Sangyong Kim ,  Jaejung Kim ,  Byounghoon Lee

IPC: H01L29/10 ,  H01L29/08

Abstract: A semiconductor device includes a first active region on a substrate, channel layers disposed on the first active region to be spaced apart from each other in a vertical direction, a first gate structure disposed on the first active region and surrounding each channel layer, and a first source/drain region on the first active region on at least one side of the first gate structure. The channel layers include first to third channel layers. The first gate structure includes a first gate electrode and a first gate dielectric layer. The first gate dielectric layer includes first to third portions surrounding the first to third channel layers, respectively. The second portion has a thickness greater than a thickness of the first portion, and the third portion has a thickness greater than the thickness of the second portion.