公开(公告)号：US11922992B2

公开(公告)日：2024-03-05

申请号：US17828200

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inseok Baek ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Seokjae Lee

IPC: G11C16/08 ,  G11C11/408 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C11/4085 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

公开(公告)号：US11349979B2

公开(公告)日：2022-05-31

申请号：US17080942

申请日：2020-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinho Mun ,  Mihwa Park ,  Donggeon Kim ,  Sungdeuk Park

IPC: H04M1/72448

Abstract: An electronic device according to an embodiment includes: a processor, and a memory configured to be operatively connected to the processor and to store a list including a plurality of profiles respectively corresponding to members recognized as users of the electronic device, wherein the memory stores, when executed, instructions that cause the processor to: acquire a usage pattern of the electronic device; compare a first profile used for configuring the electronic device among the plurality of profiles with the usage pattern; recognize a profile change based on a result of the comparison; retrieve a second profile matching the acquired usage pattern from the list based on the recognition of the profile change; and configure the electronic device using the second profile. In addition, various other embodiments are possible.

公开(公告)号：US12106795B2

公开(公告)日：2024-10-01

申请号：US17724006

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongsik Ryu ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Sangwook Park ,  Inseok Baek

IPC: G11C11/408

CPC classification number: G11C11/4085

Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

公开(公告)号：US11735248B2

公开(公告)日：2023-08-22

申请号：US17685849

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

IPC: G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4085 ,  H10B12/50 ,  H10B12/315 ,  H10B12/34

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

公开(公告)号：US20220406360A1

公开(公告)日：2022-12-22

申请号：US17685849

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

IPC: G11C11/408 ,  H01L27/108

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

公开(公告)号：US20250159868A1

公开(公告)日：2025-05-15

申请号：US18783044

申请日：2024-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Selyung Yoon ,  Daehyeon Kwon ,  Donggeon Kim ,  Bok-Yeon Won

IPC: H10B12/00 ,  H01L23/522

Abstract: A semiconductor device includes a substrate, a transistor on the substrate, a bit line structure electrically connected to the transistor, a channel layer on the bit line structure, a gate structure intersecting the bit line structure, a first conductive line electrically connecting the transistor and the bit line structure, an upper shield line overlapping the first conductive line, and side shield lines spaced apart from each other with the first conductive line interposed therebetween. The upper shield line and the side shield lines are electrically separated from the first conductive line and the bit line structure.

公开(公告)号：US20250124974A1

公开(公告)日：2025-04-17

申请号：US18618567

申请日：2024-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyeon KWON ,  Donggeon Kim ,  Bokyeon Won ,  Selyung Yoon

IPC: G11C11/4097 ,  G11C5/06 ,  G11C11/4091

Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.

公开(公告)号：US20250085858A1

公开(公告)日：2025-03-13

申请号：US18591238

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donggeon Kim ,  Myeongsik Ryu ,  Bokyeon Won ,  Seokjae Lee ,  Daehyeon Kwon ,  Kyoungmin Kim ,  Inseok Baek ,  Selyung Yoon

IPC: G06F3/06

Abstract: A bit-line sense amplifier includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer. The amplifying circuit is connected to a bit-line and a complementary bit-line, senses a voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjusts a voltage of a sensing bit-line and a complementary sensing bit-line based on the voltage difference. The equalizer is connected to the sensing bit-line, and equalizes the bit-line and the complementary bit-line to a precharge voltage, based on an equalizing signal. The equalizer includes an equalizing transistor that has a source, a gate configured to receive the equalizing signal, and a drain. The source of the equalizing transistor is connected to a wiring structure through a direct contact, and the wiring structure is configured to receive the precharge voltage.

公开(公告)号：US20240363157A1

公开(公告)日：2024-10-31

申请号：US18538260

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungmin Kim ,  Inseok Baek ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Sujin Park ,  Bokyeon Won ,  Jongmoon Yoon

IPC: G11C11/4094 ,  G11C11/4091 ,  G11C11/4099

CPC classification number: G11C11/4094 ,  G11C11/4091 ,  G11C11/4099

Abstract: A memory device includes first global bitlines adjacent to a first edge portion of a memory cell region, second global bitlines adjacent to a second edge portion of the memory cell region; dummy global bitlines in a central portion of the memory cell region, and a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines A first layer of the memory cell region is connected to a second layer of the sense amplifier region and is configured to apply a bias voltage to each of the dummy global bitlines.

公开(公告)号：US11818881B2

公开(公告)日：2023-11-14

申请号：US17709971

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek ,  Bokyeon Won

IPC: G11C11/40 ,  H10B12/00 ,  H01L25/065 ,  G11C11/408 ,  H01L29/423 ,  H01L23/498

CPC classification number: H10B12/50 ,  G11C11/4085 ,  H01L25/0652 ,  H01L29/4238 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.