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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240395807A1

    公开(公告)日：2024-11-28

    申请号：US18409884

    申请日：2024-01-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joong Suk OH ,  Ho Young KIM

    IPC: H01L27/088 ,  H01L21/762 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate with opposite first and second surfaces in a first direction, an active pattern on the first surface in a second direction, a gate electrode in a third direction on the active pattern, a source/drain on at least one side of the gate electrode and connected to the active pattern, a gate cutting structure on one side of the active pattern and cutting the gate electrode, the gate cutting structure including third and fourth surfaces opposite to each other in the first direction, and the fourth surface being coplanar with the second surface of the substrate, a power rail on the second surface of the substrate and extending in the second direction, and a via contact through the substrate, a first end of the via contact contacting the power rail, and a second end of the via contact connected to the source/drain.

    METHOD AND APPARATUS FOR PROCESSING TEXTURE
    3.
    发明申请
    METHOD AND APPARATUS FOR PROCESSING TEXTURE 有权
    处理纹理的方法和装置

    公开(公告)号：US20160110889A1

    公开(公告)日：2016-04-21

    申请号：US14815077

    申请日：2015-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hee Jun SHIM ,  Soo Jung RYU ,  Sang Heon LEE ,  Sun Min KWON ,  Ho Young KIM ,  Seong Hoon JEONG

    IPC: G06T11/00

    CPC classification number: G06T11/001

    Abstract: Provided is a method of processing a texture. The method includes acquiring texture position information in a texture image corresponding to pixel position information of pixels constituting a frame, acquiring texture classification information (TCI) representing a similarity between respective texture factors of two or more classified regions in the texture image based on the texture position information, determining an amount of texture data requested from a memory according to the TCI, and reading texture data corresponding to the determined amount of texture data based on the texture position information.

    Abstract translation: 提供了一种处理纹理的方法。 该方法包括：在与构成帧的像素的像素位置信息对应的纹理图像中获取纹理位置信息，基于纹理获取表示纹理图像中两个或更多个分类区域的各个纹理因子之间的相似度的纹理分类信息（TCI） 位置信息，根据TCI确定从存储器请求的纹理数据的量，以及基于纹理位置信息读取与确定的纹理数据量相对应的纹理数据。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20240404918A1

    公开(公告)日：2024-12-05

    申请号：US18397367

    申请日：2023-12-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joong Suk OH ,  Ho Young KIM ,  Ki Ho BAE

    IPC: H01L23/48 ,  H01L21/762 ,  H01L29/06

    Abstract: There is provided a semiconductor device in which thickness variation of a substrate is precisely controlled. The semiconductor device includes a substrate comprising cell regions, a dummy region between the cell regions, an upper surface and a lower surface opposite the upper surface in a first direction, an active pattern disposed on the upper surface of the substrate, the active pattern comprising a lower pattern extending in a second direction crossing the first direction and a plurality of sheet patterns spaced apart in the first direction from each other, the plurality of sheet patterns being disposed in the cell region, a source/drain pattern disposed between the gate structures adjacent to each other, and a buried insulating pattern penetrating the substrate and the lower pattern in the dummy region.

    NETWORK SWITCH AND METHOD WITH MATRIX AGGREGATION
    5.
    发明公开
    NETWORK SWITCH AND METHOD WITH MATRIX AGGREGATION 审中-公开

    公开(公告)号：US20240160691A1

    公开(公告)日：2024-05-16

    申请号：US18316611

    申请日：2023-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UIF (University Industry Foundation), Yonsei University

    Inventor： Ho Young KIM ,  Min Sik KIM ,  Won Woo RO ,  Se Hyun YANG

    IPC: G06F17/16 ,  G06F16/22

    CPC classification number: G06F17/16 ,  G06F16/2237

    Abstract: A method of operating a network switch for collective communication includes: receiving, via a network from external electronic devices, a first and second matrix each formatted according to a sparse matrix storage format; and generating a third matrix formatted according to the sparse matrix storage format, wherein the third matrix is generated by combining the first and second matrix according to the sparse matrix storage format, wherein, according to the sparse matrix storage format the first matrix includes first matrix positions of respective first element values and the second matrix includes second matrix positions of respective second element values, and wherein the combining includes comparing the first matrix positions with the second matrix positions.

    METHOD AND APPARATUS WITH REPEATED MULTIPLICATION
    6.
    发明公开
    METHOD AND APPARATUS WITH REPEATED MULTIPLICATION 审中-公开

    公开(公告)号：US20230385025A1

    公开(公告)日：2023-11-30

    申请号：US18187971

    申请日：2023-03-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Ho Young KIM ,  Won Woo RO ,  Se Hyun YANG ,  Dong Ho HA

    IPC: G06F7/544

    CPC classification number: G06F7/5443

    Abstract: A processing device including a first buffer storing calculation rules, a calculator including a plurality of multipliers and an adder, the multipliers configured to perform multiplication repeatedly, a second buffer storing operands, the second buffer being configured to enqueue the operands based on the calculation rules into a queue, and a counter indicating a respective number indicating a number of times a multiplication is to be performed by each of the plurality of multipliers, each multiplier of the plurality of multipliers being configured to provide a non-final multiplication result to a first path to an input of the corresponding multiplier responsive to a corresponding number of multiplications performed by the multiplier being less than the respective number, and provide a final multiplication result to a second path to the adder responsive to the corresponding number of multiplications performed by the multiplier being equal to the respective number.

    CACHE MEMORY AND METHOD OF MANAGING THE SAME
    8.
    发明申请
    CACHE MEMORY AND METHOD OF MANAGING THE SAME 有权
    高速缓存存储器及其管理方法

    公开(公告)号：US20160124866A1

    公开(公告)日：2016-05-05

    申请号：US14715683

    申请日：2015-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong Hoon JEONG ,  Woong SEO ,  Sang Heon LEE ,  Sun Min KWON ,  Ho Young KIM ,  Hee Jun SHIM

    IPC: G06F12/10 ,  G06F12/08

    CPC classification number: G06F12/0207 ,  G06F12/0607 ,  G06F12/0846 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/455

    Abstract: A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

    Abstract translation: 提供了缓存存储器及其管理方法。 管理高速缓冲存储器的方法包括：确定存储在存储体中的数据带宽的位的数量是要存储的数据中的单位数据的位数的整数倍，存储第一单位数据 响应于不是单位数据的位数的整数倍的数据带宽的比特数，存储在存储体中的第一地址的第一区域中，并存储部分第二单位数据 被存储在第一地址的第二区域中。

    SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
    9.
    发明公开
    SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开

    公开(公告)号：US20240310739A1

    公开(公告)日：2024-09-19

    申请号：US18436127

    申请日：2024-02-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoungwhan OH ,  Ho Young KIM ,  Sunghwan KIM ,  Jaekyung PARK ,  Jaehong LEE ,  Yohan CHOE

    IPC: G03F7/00 ,  G03F7/20

    CPC classification number: G03F7/70725 ,  G03F7/2043 ,  G03F7/70808

    Abstract: A substrate processing apparatus includes a substrate stage configured to support a semiconductor substrate, the substrate stage being rotatable at a predetermined angular velocity, and a discharge device above the substrate stage, the discharge device being configured to discharge a chemical solution onto the semiconductor substrate, and the discharge device including a nozzle arm movable along a radial direction from a central region of the substrate stage to a peripheral region surrounding the central region, a nozzle on the nozzle arm, the nozzle facing the substrate stage, and the nozzle being configured to discharge the chemical solution onto the semiconductor substrate at a predetermined angle relative to a surface of the semiconductor substrate, and an angle changer configured to change the predetermined angle such that the predetermined angle gradually decreases as the nozzle arm moves from the central region to the peripheral region.

    ELECTRONIC DEVICE WITH PREDETERMINED COMPRESSION SCHEMES FOR PARALLEL COMPUTING
    10.
    发明公开
    ELECTRONIC DEVICE WITH PREDETERMINED COMPRESSION SCHEMES FOR PARALLEL COMPUTING 审中-公开

    公开(公告)号：US20230153181A1

    公开(公告)日：2023-05-18

    申请号：US17896788

    申请日：2022-08-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Se Hyun YANG ,  Sungju RYU ,  Ho Young KIM

    IPC: G06F9/54 ,  G06F9/52 ,  G06N5/04

    CPC classification number: G06F9/543 ,  G06F9/52 ,  G06N5/04

    Abstract: Disclosed are electronic devices with predetermined compression schemes for parallel computing and methods thereof. An example electronic device includes cores of one or more processors, one or more memories storing instructions configured to, when executed by the cores, configure the cores to perform operations of an application executed on the electronic device, the operations including communication phases that communicate data between the cores, wherein the application includes, prior to execution of the application on the electronic device, predetermined information associating the communication phases with respective compression schemes, and apply the compression schemes corresponding to the communication phases according to the predetermined information to compress the data of the communication phases that is exchanged between the cores when executing the application.

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