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    DEVICE AND METHOD FOR ACQUIRING UPLINK SYNCHRONIZATION IN WIRELESS COMMUNICATION SYSTEM
    1.
    发明公开
    DEVICE AND METHOD FOR ACQUIRING UPLINK SYNCHRONIZATION IN WIRELESS COMMUNICATION SYSTEM 审中-公开

    公开(公告)号：US20240365397A1

    公开(公告)日：2024-10-31

    申请号：US18767136

    申请日：2024-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jonghyeuk LEE ,  Hyuncheol KIM

    IPC: H04W74/0833 ,  H04W56/00 ,  H04W74/08

    CPC classification number: H04W74/0833 ,  H04W56/0045 ,  H04W74/0866

    Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a higher data transmission rate beyond a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure includes a method carried out by a terminal in a wireless communication system. The method may comprise: receiving one or more preambles from a terminal; acquiring correlation values between a plurality of symbol groups corresponding to the one or more preambles; acquiring a timing offset value based on the correlation values, and subcarrier difference information of the plurality of symbol groups; generating uplink timing information based on the timing offset value; and transmitting, to the terminal, a random access response (RAR) including the uplink timing information.

    MEMORY DEVICES
    2.
    发明公开
    MEMORY DEVICES 审中-公开

    公开(公告)号：US20230371270A1

    公开(公告)日：2023-11-16

    申请号：US18315181

    申请日：2023-05-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Kiheun LEE ,  Daewon HA

    IPC: H10B51/30 ,  H10B51/10 ,  H01L21/28

    CPC classification number: H10B51/30 ,  H10B51/10 ,  H01L29/40111

    Abstract: A memory device may include a channel region, a conductive electrode disposed on the channel region, and a data storage structure disposed between the channel region and the conductive electrode. The data storage structure includes a first dielectric layer and a second dielectric layer disposed on the first dielectric layer, the second dielectric layer includes a ferroelectric region and a barrier dielectric region on the ferroelectric region, the ferroelectric region includes a first material, and the barrier dielectric region includes a second material formed by nitriding or oxidizing the first material.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230328950A1

    公开(公告)日：2023-10-12

    申请号：US18175445

    申请日：2023-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjun LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Mintae RYU ,  Yongjin LEE

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A semiconductor memory device includes a plurality of memory cells arranged on a substrate. Each of the plurality of memory cells may include a first transistor on the substrate and a second transistor on the first transistor. The first transistor may include a first channel region between a first source region and a first drain region, a first gate electrode, and a first gate insulating layer. The second transistor may include a pillar structure having a second drain region, a second channel region and a second source region sequentially stacked on the first gate electrode, a second gate electrode on one side of the second channel region, and a second gate insulating layer between the second channel region and the second gate electrode. The second drain region and the second source region may have a first conductivity type impurity region and a second conductivity type impurity region, respectively.

    SEMICONDUCTOR DEVICES
    4.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220199793A1

    公开(公告)日：2022-06-23

    申请号：US17443553

    申请日：2021-07-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Ilgweon KIM ,  Seokhan PARK ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L23/482

    Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities

    SEMICONDUCTOR MEMORY DEVICES
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220367479A1

    公开(公告)日：2022-11-17

    申请号：US17716215

    申请日：2022-04-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Dongsoo WOO ,  Sungwon YOO

    IPC: H01L27/108 ,  H01L29/423 ,  H01L29/792

    Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220216239A1

    公开(公告)日：2022-07-07

    申请号：US17503713

    申请日：2021-10-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungwon YOO ,  Yongseok KIM ,  Ilgweon KIM ,  Hyuncheol KIM ,  Hyeoungwon SEO ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L27/12 ,  H01L27/13 ,  H01L25/065 ,  H01L25/18 ,  H01L21/84

    Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.

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