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    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    2.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230413545A1

    公开(公告)日：2023-12-21

    申请号：US18365915

    申请日：2023-08-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Min Hwang ,  Joon Sung Lim ,  Bum Kyu Kang ,  Jae Ho Ahn

    IPC: H10B41/27 ,  H01L23/535

    CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L23/535

    Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

    Nonvolatile memory device and method for fabricating the same
    6.
    发明授权
    Nonvolatile memory device and method for fabricating the same 有权

    公开(公告)号：US11315947B2

    公开(公告)日：2022-04-26

    申请号：US16890115

    申请日：2020-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae Ho Ahn ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Bum Kyu Kang ,  Sang Don Lee

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556

    Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

    Nonvolatile memory device
    7.
    发明授权
    Nonvolatile memory device 有权

    公开(公告)号：US12232318B2

    公开(公告)日：2025-02-18

    申请号：US17726899

    申请日：2022-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae Ho Ahn ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Bum Kyu Kang ,  Sang Don Lee

    IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

    Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

    Semiconductor memory device and electronic system including the same
    8.
    发明授权
    Semiconductor memory device and electronic system including the same 有权

    公开(公告)号：US11844211B2

    公开(公告)日：2023-12-12

    申请号：US17340148

    申请日：2021-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

    IPC: H10B41/27 ,  H01L23/538 ,  H01L25/065 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L23/5384 ,  H01L25/0657 ,  H10B43/27

    Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

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