公开(公告)号：US10600805B2

公开(公告)日：2020-03-24

申请号：US16157684

申请日：2018-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Park ,  Jong-Min Lee ,  Seon-Kyung Kim ,  Kee-Jeong Rho ,  Jin-hyun Shin ,  Jong-Hyun Park ,  Jin-Yeon Won

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

公开(公告)号：US20190139984A1

公开(公告)日：2019-05-09

申请号：US16220836

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon KIM ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC: H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

公开(公告)号：US10700088B2

公开(公告)日：2020-06-30

申请号：US16220836

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC: H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.