公开(公告)号：US20230281436A1

公开(公告)日：2023-09-07

申请号：US18197093

申请日：2023-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joon KIM ,  Jinseok KIM ,  Taesu KIM

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/049

CPC classification number: G06N3/063 ,  G06F17/16 ,  G06N3/049

Abstract: A method for processing data based on a neural network including a first layer including axons and a second layer including neurons, includes receiving synaptic weights between the first layer and the second layer; generating presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, from the synaptic weights; and storing the presynaptic weights and the postsynaptic weights in a synapse memory.

公开(公告)号：US20200264773A1

公开(公告)日：2020-08-20

申请号：US16795334

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokwon KIM ,  Jinseok KIM ,  Dami JEON

IPC: G06F3/0488 ,  G06F3/041

Abstract: An electronic device includes a display, at least one processor, and a memory. The memory is configured to store instructions that when executed enable the processor to control the display to display an execution screen of application stored in the memory. The instructions also enable the processor to identify an occurrence of an event for displaying an execution screen of the virtual keyboard application while displaying the execution screen of the application. The instructions further enable the processor to, based on the occurrence of the event, identify at least one color value related to the at least one element included in the execution screen of the application, and control the display to display the execution screen of the virtual keyboard application corresponding to the at least one identified color value.

公开(公告)号：US20200341629A1

公开(公告)日：2020-10-29

申请号：US16857692

申请日：2020-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyup LEE ,  Jinseok KIM ,  Minjeong MOON ,  Minjung MOON ,  Myojin BANG ,  Seoyoung YOON ,  Dami JEON ,  Jaegi HAN ,  Jiyoon HEO

IPC: G06F3/0488 ,  G06F3/0481

Abstract: Disclosed is an electronic device including a display device including a touch sensor and a processor electrically connected to the touch sensor and the display device, wherein the processor is configured to control the electronic device to: display content and a cursor on a first area of the display device, display a touch pad user interface configured to receive a touch input on a second area of the display device, and control the cursor on the first area based on the touch input received through the touch pad user interface displayed on the second area.

公开(公告)号：US20230260568A1

公开(公告)日：2023-08-17

申请号：US18303309

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinseok KIM ,  Yulhwa KIM ,  Jae-Joon KIM ,  Hyungjun KIM

IPC: G11C11/412 ,  G06N3/08 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412 ,  G06N3/08 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

公开(公告)号：US20200184315A1

公开(公告)日：2020-06-11

申请号：US16561378

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Sungho KIM ,  Yulhwa KIM ,  Hyungjun KIM ,  Jae-Joon KIM ,  Jinseok KIM

IPC: G06N3/04 ,  G06N3/08

Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.

公开(公告)号：US20250014638A1

公开(公告)日：2025-01-09

申请号：US18891682

申请日：2024-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinseok KIM ,  Yulhwa KIM ,  Jae-Joon KIM ,  Hyungjun KIM

IPC: G11C11/412 ,  G06N3/08 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

公开(公告)号：US20230118943A1

公开(公告)日：2023-04-20

申请号：US18081837

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joon KIM ,  Jinseok KIM ,  Taesu KIM

IPC: G06N3/063 ,  G06N5/04 ,  G06N3/08

Abstract: A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.

公开(公告)号：US20190138892A1

公开(公告)日：2019-05-09

申请号：US16170081

申请日：2018-10-25

Applicant: Samsung Electronics Co., Ltd. ,  Postech Academy-Industry Foundation

Inventor： Sungho KIM ,  Jinseok KIM ,  Yulhwa KIM ,  Jaejoon KIM ,  Dusik PARK

IPC: G06N3/063 ,  G06N3/04

Abstract: A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.