公开(公告)号：US11442522B2

公开(公告)日：2022-09-13

申请号：US16823483

申请日：2020-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkyu Kim ,  Jonglae Park ,  Hyunju Kang ,  Jungwook Kim

IPC: G06F1/3203 ,  H01L27/112 ,  G06F1/12 ,  G06F1/3296 ,  G06F1/324

Abstract: There is provided a method of controlling performance boosting of a semiconductor device. According to the method, input of a user is monitored. A performance of the semiconductor device is boosted by consecutively executing a plurality of boosting policies associated with a plurality of macros based on an input event associated with the input of the user and available energy during a boosting interval. Boosting level in each of the boosting policies may be adaptively determined based on the boosting level and the amount of usage of the semiconductor device used in the previous boosting policy and the boosting policies are consecutively executed. Accordingly, improved and/or optimal performance boosting can be provided to the semiconductor device and at the same time, a waste of power can be mitigated and/or prevented.

公开(公告)号：US20240086234A1

公开(公告)日：2024-03-14

申请号：US18196749

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonglae Park ,  Eunok JO ,  Bumgyu PARK ,  Seyeong BYEON ,  Daeyeong LEE

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: An electronic device includes: a plurality of processing cores and a memory including a plurality of task queues respectively corresponding to the plurality of processing cores and a plurality of task relation tables respectively corresponding to a plurality of tasks. Each of the plurality of task relation tables includes: one or more entries representing a mapping relationship between an identifier of a waker task that wakes up a wakee task, and an occurrence count that is a number of times the wakee task is woken up by the waker task. At least one of the plurality of processing cores is configured to: execute a scheduler, search for a task set includes related tasks, based on the plurality of task relation tables, store a subset of tasks of the task set in at least one of the plurality of task queues, and schedule the task set.

公开(公告)号：US20240320035A1

公开(公告)日：2024-09-26

申请号：US18400663

申请日：2023-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu Kim ,  Bumgyu Park ,  Sangil Park ,  Jonglae Park ,  Eunok Jo

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3838

Abstract: A method to analyze tasks includes: obtaining, by a second device from a first device, log data including a plurality of log entries corresponding to a plurality of tasks executed in the first device; grouping the plurality of log entries into a plurality of groups based on at least one of task identifier information in each of the plurality of log entries and a type of each of the plurality of log entries; determining execution information and dependency information corresponding to each of the plurality of tasks, based on summing values extracted from log entries in each of the plurality of groups; and generating a task dependency graph indicating dependency information between the plurality of tasks and identifier information about each of the plurality of tasks, based on the execution information and the dependency information.

公开(公告)号：US11768702B2

公开(公告)日：2023-09-26

申请号：US17112008

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Seok ,  Choonghoon Park ,  Byungsoo Kwon ,  Bumgyu Park ,  Jonglae Park ,  Junhwa Seo ,  Youngcheol Shin ,  Youngtae Lee

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/50 ,  G06F9/505 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/541 ,  G06F9/4893

Abstract: An apparatus and a method for scheduling a task in an electronic device including a heterogeneous multi-processor are provided. The electronic device includes a memory and a processor operatively connected to the memory and including a plurality of heterogeneous cores. The processor may be configured to identify, when a task to be scheduled occurs, a scheduling group having the task among a plurality of predefined scheduling groups, and to perform scheduling for the task, based on the identified scheduling group having the task and a priority of the task.

公开(公告)号：US20240320061A1

公开(公告)日：2024-09-26

申请号：US18528160

申请日：2023-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumgyu PARK ,  Jonglae Park ,  Sangkyu Kim ,  Eunok Jo

IPC: G06F9/52

CPC classification number: G06F9/526

Abstract: Provided is a method of controlling access a shared resources when executing a first process that acquires a lock on the shared resource and adding a second process to a waiting queue. A determination is made on whether to deactivate preemption for the processor based on a priority of the second process, and based on determining to deactivate preemption for the processor, executing the first process until execution of the first process on the shared resource is completed, then retrieving the lock from the first process after execution of the first process on the shared resource is completed and reactivating preemption for the processor.

公开(公告)号：US11243604B2

公开(公告)日：2022-02-08

申请号：US16861383

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonglae Park ,  Youngtae Lee ,  Choonghoon Park ,  Hyunchul Seok ,  Kwanjin Jung

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/324

Abstract: Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.

公开(公告)号：US12001880B2

公开(公告)日：2024-06-04

申请号：US16822373

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumgyu Park ,  Jonglae Park

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/50 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/4881 ,  G06F9/30083 ,  G06F9/4837 ,  G06F9/485 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/542 ,  G06F9/546 ,  G06F11/3024 ,  G06F11/3419 ,  G06F11/3433

Abstract: A method of controlling an operation of a multi-core system including a plurality of processor cores, includes, monitoring task execution delay times with respect to tasks respectively assigned to the plurality of processor cores, monitoring core execution delay times with respect to the plurality of processor cores and controlling an operation of the multi-core system based on the task execution delay times and the core execution delay times.

公开(公告)号：US20220308920A1

公开(公告)日：2022-09-29

申请号：US17529854

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyeong Byeon ,  Jonglae Park ,  Hojin Kim ,  Gurnrack Moon ,  Daeyeong Lee ,  Youngtae Lee

IPC: G06F9/48

Abstract: A task scheduling method for a central processing unit (CPU) including a plurality of cores includes receiving a task processing request, obtaining first feedback data for the plurality of cores, obtaining second feedback data for an external intellectual property (IP) block outside the CPU, and assigning a task to at least one of the plurality of cores based on the first feedback data and the second feedback data.

公开(公告)号：US20210081027A1

公开(公告)日：2021-03-18

申请号：US16861383

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonglae Park ,  Youngtae Lee ,  Choonghoon Park ,  Hyunchul Seok ,  Kwanjin Jung

IPC: G06F1/3296 ,  G06F1/324

Abstract: Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.