公开(公告)号：US20230240073A1

公开(公告)日：2023-07-27

申请号：US18063878

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhwan SON ,  Miso KIM ,  Joongshik SHIN ,  Minjae OH

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B41/50 ,  H10B43/50 ,  H01L21/28

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B41/50 ,  H10B43/50 ,  H01L29/40117

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

公开(公告)号：US20220173118A1

公开(公告)日：2022-06-02

申请号：US17354445

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjun KANG ,  Byunggon PARK ,  Joongshik SHIN

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor device including a gate electrode structure on a substrate and including gate electrodes spaced apart from each other in a first direction, each gate electrode extending in a second direction; a memory channel structure extending through the gate electrode structure on the substrate, the memory channel structure including a channel extending in the first direction; a charge storage structure surrounding an outer sidewall of the channel; a first filling pattern filling an inner space formed by the channel; and a first capping pattern on the channel and the first filling pattern; and a dummy charge storage structure extending through the gate electrode structure on the substrate, the dummy charge storage structure including a second filling pattern extending in the first direction; a dummy charge storage structure surrounding an outer sidewall of the second filling pattern; and a second capping pattern on the second filling pattern.

公开(公告)号：US20240107763A1

公开(公告)日：2024-03-28

申请号：US18207774

申请日：2023-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghee CHUNG ,  Hyeongjin KIM ,  Joongshik SHIN ,  Jeehoon HAN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06541

Abstract: A semiconductor device includes a source structure including a plate layer and first and second horizontal conductive layers stacked in order on the plate layer, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the source structure, a channel structure penetrating through the gate electrodes, extending in the first direction, and including a channel layer in contact with the first horizontal conductive layer, and a separation region penetrating through the gate electrodes and extending in the first direction and in a second direction perpendicular to the first direction, wherein the first horizontal conductive layer extends horizontally below the separation region and has a seam overlapping the separation region in the first direction.

公开(公告)号：US20220344267A1

公开(公告)日：2022-10-27

申请号：US17861700

申请日：2022-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Joongshik SHIN ,  Kwangsoo KIM

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US20220238550A1

公开(公告)日：2022-07-28

申请号：US17488576

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongshik SHIN

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor device including: a horizontal wiring layer; a stack structure including a plurality of mold layers and a plurality of wiring layers alternately stacked on the horizontal wiring layer; a plurality of channel structures extending through the stack structure; and a plurality of separation patterns extending through the stack structure, wherein each of the plurality of separation patterns includes a plurality of first areas and a plurality of second areas adjacent to the plurality of first areas, wherein each of the plurality of first areas has a smaller width than each of the plurality of second areas.

公开(公告)号：US20250070029A1

公开(公告)日：2025-02-27

申请号：US18943201

申请日：2024-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Joongshik SHIN ,  Kwangsoo KIM

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US20220093630A1

公开(公告)日：2022-03-24

申请号：US17241232

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beyounghyun KOH ,  Seungmin SONG ,  Joongshik SHIN ,  Yongjin KWON ,  Jinhyuk KIM ,  Hongik SON

IPC: H01L27/11575 ,  H01L23/535 ,  H01L23/00 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

公开(公告)号：US20210320125A1

公开(公告)日：2021-10-14

申请号：US17162408

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon SHIN ,  Kangmin KIM ,  Kyeongjin PARK ,  Seungmin SONG ,  Joongshik SHIN ,  Geunwon LIM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522

Abstract: A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

公开(公告)号：US20250107093A1

公开(公告)日：2025-03-27

申请号：US18973034

申请日：2024-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongshik SHIN

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/10

Abstract: A semiconductor device including: a horizontal wiring layer; a stack structure including a plurality of mold layers and a plurality of wiring layers alternately stacked on the horizontal wiring layer; a plurality of channel structures extending through the stack structure; and a plurality of separation patterns extending through the stack structure, wherein each of the plurality of separation patterns includes a plurality of first areas and a plurality of second areas adjacent to the plurality of first areas, wherein each of the plurality of first areas has a smaller width than each of the plurality of second areas.

公开(公告)号：US20240381641A1

公开(公告)日：2024-11-14

申请号：US18435342

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungeun PARK ,  Solmi KWAK ,  Jinhyuk KIM ,  Hyeongjin KIM ,  Jeongyong SUNG ,  Minsoo SHIN ,  Seungjun SHIN ,  Joongshik SHIN ,  Sunghee CHUNG ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: A vertical memory device may include a common source plate on a substrate including a first region and a second region; gate pattern structures on the common source plate and extending from the first region to the second region, wherein the gate pattern structures include gate patterns and first insulation layers, and wherein the adjacent gate pattern structures are spaced apart from each other; first separation patterns filling first openings between the adjacent gate pattern structures on the first region; second separation patterns filling second openings between the adjacent gate pattern structures on the second region, wherein at least one of the second separation patterns is connected to at least one of the first separation patterns, and wherein the second separation pattern has a shape different from a shape of the first separation pattern; and channel structures passing through the gate pattern structures on the first region.