公开(公告)号：US20240206159A1

公开(公告)日：2024-06-20

申请号：US18454105

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjung Lee ,  Dongsik Kong ,  Junsoo Kim ,  Junbum Lee ,  Jinseong Lee

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/053 ,  H10B12/34

Abstract: Integrated circuit devices may include a substrate including a word line trench extending longitudinally in a first horizontal direction, a gate dielectric film extending along an inner surface of the word line trench, a word line in a lower portion of the word line trench on the gate dielectric film and extending longitudinally in the first horizontal direction, and an insulating capping pattern in an upper portion of the word line trench on the word line and extending longitudinally in the first horizontal direction. The word line may include a work-function control conductive plug including a conductive metal nitride that include a metal dopant, and the work-function control conductive plug includes a top surface in contact with a bottom surface of the insulating capping pattern, a sidewall in contact with the gate dielectric film, and a bottom surface in contact with a monolithic layer.

公开(公告)号：US20250040124A1

公开(公告)日：2025-01-30

申请号：US18442274

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsik Kong ,  Sungho Jang ,  Junsoo Kim ,  Junbum Lee ,  Jaehyun Choi ,  Ilgweon Kim ,  Jeonghoon Oh

IPC: H10B12/00

Abstract: A gate structure includes a gate electrode on a substrate, the gate electrode including a lower portion and an upper portion sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate; a spacer structure including a second spacer and a first spacer sequentially stacked in a second direction substantially parallel to the upper surface of the substrate on a sidewall of the upper portion of the gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the lower portion of the gate electrode and an outer sidewall of the spacer structure; wherein a cross-section of the first spacer has a shape of an “L”, and wherein the second spacer includes a material that is configured to induce a dipole at an interface of the first spacer and the gate insulation pattern.