公开(公告)号：US20220361339A1

公开(公告)日：2022-11-10

申请号：US17591734

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwa KIM ,  Junso PAK ,  Heeseok LEE ,  Moonseob JEONG ,  Jisoo HWANG

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H05K1/02

Abstract: A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.

公开(公告)号：US20250157867A1

公开(公告)日：2025-05-15

申请号：US18883053

申请日：2024-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongkook KIM ,  Heungkyu KWON ,  Youngchul KIM ,  Choonheung LEE ,  Donghyun CHA ,  Junghwa KIM ,  Junso PAK ,  Kyounghoon LEE ,  Jaegwon JANG ,  Hangchul CHOI ,  Heejung CHOI ,  Kyojin HWANG

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/18 ,  H05K1/18 ,  H10B80/00

Abstract: A semiconductor package that includes an upper package including a first package substrate, a first semiconductor chip mounted on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board (PCB) on which the upper package is mounted in a central region; and a stiffener positioned on a top surface of the PCB and including an opening. A top surface of the PCB contacts a bottom surface of the stiffener in at least part of edge regions of the PCB. In the central region of the PCB and in edge regions other than the at least part of edge regions of the PCB, a top surface of the PCB is apart from the bottom surface of the stiffener in a vertical direction, and the opening of the stiffener overlaps the upper package in the vertical direction.

公开(公告)号：US20220254870A1

公开(公告)日：2022-08-11

申请号：US17344475

申请日：2021-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyangsook LEE ,  Junghwa KIM ,  Eunha LEE ,  Jeonggyu SONG ,  Jooho LEE ,  Myoungho JEONG

IPC: H01L49/02 ,  H01L29/08

Abstract: Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a , , or direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

公开(公告)号：US20220077064A1

公开(公告)日：2022-03-10

申请号：US17307037

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejung CHOI ,  Heeseok LEE ,  Junghwa KIM

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.

公开(公告)号：US20220140147A1

公开(公告)日：2022-05-05

申请号：US17459529

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dukhyun CHOE ,  Hyangsook LEE ,  Junghwa KIM ,  Eunha LEE ,  Sanghyun JO ,  Jinseong HEO

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A thin film structure includes a substrate; and a material layer having a fluorite structure, the material layer on the substrate and comprising crystals of which crystal orientation is aligned in a normal direction of the substrate. The material layer may have ferroelectricity. The material layer may include the crystals of which the crystal orientation is aligned in the normal direction of the substrate among all crystals of the material layer in a dominant ratio.

公开(公告)号：US20210355380A1

公开(公告)日：2021-11-18

申请号：US17238538

申请日：2021-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jun PARK ,  Junghwa KIM ,  Tae Gon KIM ,  Taekhoon KIM ,  Young Mo SUNG ,  Nayoun WON ,  Dongjin YUN ,  Mi Hye LIM ,  Shin Ae JUN ,  Hyeonsu HEO

IPC: C09K11/56

Abstract: A quantum dot including a semiconductor nanocrystal core including Group III-V compound, a first semiconductor nanocrystal shell disposed on the semiconductor nanocrystal core, the first semiconductor nanocrystal shell including zinc and selenium, and a second semiconductor nanocrystal shell disposed on the first semiconductor nanocrystal shell, the second semiconductor nanocrystal shell including zinc and sulfur, and a composite/electronic device. The quantum dot does not include cadmium and the first semiconductor nanocrystal shell includes a polyvalent metal dopant at an interface with the second semiconductor nanocrystal shell.

公开(公告)号：US20210193811A1

公开(公告)日：2021-06-24

申请号：US16923514

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Eunha LEE ,  Junghwa KIM ,  Hyangsook LEE ,  Sanghyun JO ,  Jinseong HEO

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L49/02 ,  H01L27/108

Abstract: Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.

公开(公告)号：US20170324050A1

公开(公告)日：2017-11-09

申请号：US15262302

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam KWON ,  Junghwa KIM ,  Jaewon JANG

IPC: H01L51/05 ,  H01G4/005 ,  H01G4/04 ,  H01L29/51

CPC classification number: H01L51/052 ,  H01G4/005 ,  H01G4/04 ,  H01L29/51

Abstract: A dielectric and a dielectric ink include a dielectric material. The dielectric material includes ceramide or a ceramide derivative. A capacitor and a transistor may include the dielectric material. A device may include at least one of a capacitor and a transistor that includes the dielectric material. A dielectric that includes ceramide or a ceramide derivative may be configured to provide dielectric performance in a bio field. The effect on a human body by the dielectric may be reduced, based on the dielectric material of the dielectric including ceramide or a ceramide derivative.

公开(公告)号：US20170139514A1

公开(公告)日：2017-05-18

申请号：US15351788

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mi Jeong KIM ,  Chan KWAK ,  Junghwa KIM ,  Dong Su KO ,  Kwanghee KIM ,  Jiye KIM

IPC: G06F3/041 ,  C22F1/14 ,  B32B15/08 ,  B22F1/00 ,  G06F3/045 ,  B32B15/02

CPC classification number: G06F3/0412 ,  B22F1/0025 ,  B22F2301/255 ,  B22F2304/05 ,  B32B15/02 ,  B32B15/08 ,  B32B2307/202 ,  B32B2457/208 ,  C22F1/14 ,  G06F3/045 ,  G06F2203/04102 ,  G06F2203/04103 ,  H01B1/02 ,  H01B1/22

Abstract: An electrical conductor includes a substrate; and a conductive layer disposed on the substrate and including a plurality of silver nanowires, wherein the silver nanowires exhibit a main peak assigned to a (111) crystal plane in an X-ray diffraction spectrum thereof, and a 2θ full width at half maximum (FWHM) of the main peak after Gaussian fitting is less than about 0.40 degrees.

公开(公告)号：US20170106636A1

公开(公告)日：2017-04-20

申请号：US15212785

申请日：2016-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SAMSUNG SDI CO., LTD.

Inventor： A Ra JO ,  Chanjae AHN ,  Sungwon CHOI ,  Byunghee SOHN ,  Seung Bum Joseph CHUN ,  Sung Woo HONG ,  Junghwa KIM ,  Da Eun YU

IPC: B32B27/34 ,  B32B27/38 ,  B32B27/28

CPC classification number: B32B27/34 ,  B32B7/04 ,  B32B27/08 ,  B32B27/281 ,  B32B27/308 ,  B32B27/38 ,  B32B27/40 ,  B32B2250/02 ,  B32B2250/03 ,  B32B2250/24 ,  B32B2255/00 ,  B32B2307/40 ,  B32B2307/412 ,  B32B2307/536 ,  B32B2307/54 ,  B32B2307/546 ,  B32B2307/584 ,  B32B2307/732 ,  B32B2451/00 ,  B32B2457/00 ,  B32B2457/20 ,  B32B2457/202 ,  B32B2457/204 ,  B32B2457/206

Abstract: A window for a display device including: a plastic substrate including a poly(imide-amide) copolymer, which is a reaction product of a reagent combination of 4,4′-hexafluoroisopropylidene diphthalic anhydride, 3,3′,4,4′-biphenyltetracarboxylic dianhydride, 2,2′-bis-trifluoromethyl-4,4′-biphenyldiamine, and terephthaloyl chloride, and a hard coating layer disposed on at least one side of the plastic substrate, wherein the plastic substrate has pencil scratch hardness of greater than or equal to 3H when measured according to an ASTM D3363 standard at a vertical load of about 0.5 kilograms, and a peak intensity ratio A2/A1 of a peak intensity A2 at a position of about 23.5° in 2θ to a peak intensity A1 at a position of about 15.5° in 2θ of an X-ray diffraction spectrum is greater than or equal to about 0.8.