公开(公告)号：US09865581B2

公开(公告)日：2018-01-09

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

公开(公告)号：US09236349B2

公开(公告)日：2016-01-12

申请号：US13943828

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Ho-Jin Lee ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC: H01L23/538 ,  H01L23/485 ,  H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/6836 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract translation: 提供了包括通孔结构和再分配结构的半导体器件。 半导体器件可以包括在衬底的第一侧上的内部电路，垂直穿过衬底以与内部电路中的一个电连接的通孔结构，在衬底的第二侧上的再分配结构，并且电连接到通孔 通孔结构，以及在基板的第二面和再分布结构之间的绝缘层。 再分布结构可以包括再分配阻挡层和再分布金属层，再分布阻挡层可以在再分布金属层的底表面上延伸并且可以部分地围绕再分布金属层的一侧。

公开(公告)号：US20140110894A1

公开(公告)日：2014-04-24

申请号：US13964433

申请日：2013-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Gilheyun Choi

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L21/78 ,  H01L2224/81

Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.

Abstract translation: 晶片载体包括具有设置在基部的中心处的空腔的基部和沿着基部的边缘延伸并远离基部的边缘的外侧壁以限定空腔。 空腔构造成填充有粘合剂层。 晶片载体构造成在基底的空腔中与粘合剂层结合到晶片，使得外侧壁面向并与晶片的边缘接触并且空腔面向晶片的中心。

公开(公告)号：US20130200526A1

公开(公告)日：2013-08-08

申请号：US13756833

申请日：2013-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangjin Moon ,  SuKyoung Kim ,  Kunsang Park ,  Byung Lyul Park ,  Sukchul Bang ,  Jin Ho An ,  Kyu-Ha Lee ,  Dosun Lee ,  Gilheyun Choi

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract translation: 提供具有通孔的半导体器件及其制造方法。 所述方法可以包括形成至少部分地穿透基板的通孔，所述通孔具有设置在所述基板的顶表面上的入口，形成通孔绝缘层以保形地覆盖所述通孔的内表面，形成缓冲器 所述缓冲层由收缩性优于所述通孔绝缘层的材料形成，形成贯通电极以填充所述通孔，所述通孔设置在所述通孔绝缘层上， 与缓冲层一起凹陷基底的底表面以露出通孔。

公开(公告)号：US20170053882A1

公开(公告)日：2017-02-23

申请号：US15209298

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Kyu-Ha Lee ,  Jinho Chun ,  Byunglyul Park ,  Jinho An

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31 ,  H01L25/11

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/05 ,  H01L24/08 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/06181 ,  H01L2224/08059 ,  H01L2224/08111 ,  H01L2224/13022 ,  H01L2224/17181 ,  H01L2225/0652 ,  H01L2225/06541

Abstract: An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.

Abstract translation: 电子器件包括在衬底上的上绝缘层。 上部再分配结构嵌入在上绝缘层中。 上再分配结构包括上接触部分，上焊盘部分和上接触部分和上焊盘部分之间的上线部分。 钝化层位于上绝缘层和上再分布结构上。 上开口构造成穿过钝化层并暴露上焊盘部分。 上部焊盘部分和上部接触部分的垂直厚度大于上部分部分的垂直厚度。

公开(公告)号：US20170033032A1

公开(公告)日：2017-02-02

申请号：US15163995

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Hyung-Jun Jeon ,  Jum-Yong Park ,  Byung-Lyul Park ,  Ji-Soon Park ,  Jin-Ho An ,  Jin-Ho Chun

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/532 ,  H01L21/768 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76852 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2223/5446 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06151 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

Abstract translation: 半导体器件包括具有管芯区域和围绕管芯区域的划线区域的衬底，穿过管芯区域中的衬底的多个通孔结构，一部分通孔结构暴露在衬底的表面上，以及 保护层图案结构，其设置在所述基板的表面上，所述表面包围所述通孔结构的所述暴露部分的侧壁，并且具有覆盖所述划线区域的与所述通孔结构相邻的至少一部分的突出部分。

公开(公告)号：US20150093896A1

公开(公告)日：2015-04-02

申请号：US14566828

申请日：2014-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

Abstract translation: 本发明构思提供了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面开口并部分地穿透衬底的通孔，在通孔的底表面上形成具有第一厚度的通孔绝缘层，并且小于第一厚度的第二厚度 在通孔的内侧壁上的厚度，在形成通孔绝缘层的通孔中形成通孔，并使基板的底表面凹陷以露出通孔。 形成通孔绝缘层可以包括在基板上形成可流动层，并且将可流动层转化为具有第一厚度的第一可流动化学气相沉积层，其在通孔的底表面上。

公开(公告)号：US08941216B2

公开(公告)日：2015-01-27

申请号：US13749727

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

Abstract translation: 本发明构思提供了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面开口并部分地穿透衬底的通孔，在通孔的底表面上形成具有第一厚度的通孔绝缘层，并且小于第一厚度的第二厚度 在通孔的内侧壁上的厚度，在形成通孔绝缘层的通孔中形成通孔，并使基板的底表面凹陷以露出通孔。 形成通孔绝缘层可以包括在基板上形成可流动层，并且将可流动层转化为具有第一厚度的第一可流动化学气相沉积层，其在通孔的底表面上。

公开(公告)号：US20130207241A1

公开(公告)日：2013-08-15

申请号：US13749727

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheun Choi

IPC: H01L23/522

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

Abstract translation: 本发明构思提供了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面开口并部分地穿透衬底的通孔，在通孔的底表面上形成具有第一厚度的通孔绝缘层，并且小于第一厚度的第二厚度 在通孔的内侧壁上的厚度，在形成通孔绝缘层的通孔中形成通孔，并使基板的底表面凹陷以露出通孔。 形成通孔绝缘层可以包括在基板上形成可流动层，并且将可流动层转化为具有第一厚度的第一可流动化学气相沉积层，其在通孔的底表面上。

公开(公告)号：US09799619B2

公开(公告)日：2017-10-24

申请号：US15209298

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Kyu-Ha Lee ,  Jinho Chun ,  Byunglyul Park ,  Jinho An

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/11 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/05 ,  H01L24/08 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/06181 ,  H01L2224/08059 ,  H01L2224/08111 ,  H01L2224/13022 ,  H01L2224/17181 ,  H01L2225/0652 ,  H01L2225/06541

Abstract: An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.