公开(公告)号：US20230292490A1

公开(公告)日：2023-09-14

申请号：US18081905

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin Lee ,  Yongseok Kim ,  Mintae Ryu ,  Huije Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.

公开(公告)号：US20250016992A1

公开(公告)日：2025-01-09

申请号：US18763801

申请日：2024-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juho Lee ,  Mintae Ryu ,  Youngseok Park ,  Seongjae Byeon ,  Younggeun Song

IPC: H10B12/00

Abstract: A semiconductor memory device includes a substrate, a conductive line disposed on the substrate, a horizontal channel portion extending in a first direction on the conductive line and partially covering the conductive line, a separation insulating layer disposed on the horizontal channel portion, a gate insulating layer including a first portion on the conductive line and a second portion that extends in a second direction that is perpendicular to the substrate, a vertical channel portion between the gate insulating layer and the separation insulating layer, the vertical channel portion extending in the second direction, and a spacer on the first portion of the gate insulating layer. A first material included in the horizontal channel portion is different from a second material included in the vertical channel portion.

公开(公告)号：US12199127B2

公开(公告)日：2025-01-14

申请号：US17528237

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongsoon Kang ,  Mintae Ryu ,  Minsu Lee ,  Wonsok Lee

IPC: H01L27/146 ,  H01L27/148

Abstract: An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.

公开(公告)号：US12166132B2

公开(公告)日：2024-12-10

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Mintae Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Hyunmog Park ,  Kiseok Lee

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US20220384661A1

公开(公告)日：2022-12-01

申请号：US17578893

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Kiseok Lee ,  Wonsok Lee ,  Mintae Ryu ,  Hyunmog Park ,  Woobin Song ,  Sungwon Yoo

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.