公开(公告)号：US20230046782A1

公开(公告)日：2023-02-16

申请号：US17700879

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Un-Byoung Kang ,  Sechul Park ,  Hyojin Yun ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/56 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers includes first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips.

公开(公告)号：US20250079378A1

公开(公告)日：2025-03-06

申请号：US18949707

申请日：2024-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoungjoo Lee ,  Unbyoung Kang ,  Sechul Park ,  Sangsick Park ,  Hyojin Yun ,  Teakhoon Lee ,  Juil Choi

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.

公开(公告)号：US12176313B2

公开(公告)日：2024-12-24

申请号：US17652782

申请日：2022-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoungjoo Lee ,  Unbyoung Kang ,  Sechul Park ,  Sangsick Park ,  Hyojin Yun ,  Teakhoon Lee ,  Juil Choi

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.

公开(公告)号：US12119331B2

公开(公告)日：2024-10-15

申请号：US17677453

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Heewon Kim ,  Sechul Park ,  Jongho Park ,  Junyoung Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L23/49833 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08237 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

公开(公告)号：US20240088094A1

公开(公告)日：2024-03-14

申请号：US18314287

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Yun ,  Unbyoung Kang ,  Seokbong Park ,  Sechul Park ,  Junyoung Park ,  Teahwa Jeong ,  Juil Choi

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5387 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a substrate including a first region, a second region in contact with the first region with the first and second regions stacked in a first direction, and a third region extending from the first and second regions in a second direction, perpendicular to the first direction, to connect the first and second regions to each other in bent form, a first semiconductor chip on a first side opposite to a second side of the first region in contact with the second region, a second semiconductor chip on a first side opposite to a second side of the second region in contact with the first region, a first molding member on the first region and covering at least a portion of the first semiconductor chip, and a second molding member on the second region and covering at least a portion of the second semiconductor chip.

公开(公告)号：US20230038603A1

公开(公告)日：2023-02-09

申请号：US17810036

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juil Choi ,  Unbyoung Kang ,  Sechul Park ,  Hyojin Yun ,  Teahwa Jeong ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L21/66

Abstract: A semiconductor package includes a semiconductor chip including a second bonding insulating layer surrounding at least a portion of each of a first bonding pad structure and a second bonding pad structure, in which the first bonding pad structure includes a first contact portion, a first bonding pad, and a first seed layer disposed between the first bonding pad and the first contact portion and extending in a first direction, the second bonding pad structure includes a second contact portion, a second bonding pad, and a second seed layer disposed between the second bonding pad and the second contact portion and extending in the first direction, and the second bonding insulating layer is in contact with a side surface of each of the first and second seed layers and the first and second bonding pads.

公开(公告)号：US20230011778A1

公开(公告)日：2023-01-12

申请号：US17652782

申请日：2022-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoungjoo Lee ,  Unbyoung Kang ,  Sechul Park ,  Sangsick Park ,  Hyojin Yun ,  Teakhoon Lee ,  Juil Choi

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.