公开(公告)号：US09786675B2

公开(公告)日：2017-10-10

申请号：US15043640

申请日：2016-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Zhiliang Xia ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Seunghyun Lim

IPC: H01L29/788 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7923

Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

公开(公告)号：US12167158B2

公开(公告)日：2024-12-10

申请号：US18062853

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwa Paik ,  Cyuyeol Rhee ,  Kyungil Kim ,  Jaehong Kim ,  Jinwoo Kim ,  Seunghyun Lim ,  Sanghyun Cho

IPC: H04N25/78 ,  H04N25/709

Abstract: An analog-to-digital converting circuit includes a first amplifier configured to output a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier configured to generate a second output signal based on the first output signal. The second amplifier includes a first transistor configured to provide a power supply voltage to a first output node in response to the first output signal, a second transistor connected with a capacitor through a bias node, wherein the second transistor is configured to turn on in response to an auto-zero signal, a current source connected with the first transistor through the first output node, the current source configured to generate a power current based on a voltage level of the bias node, and a third transistor connected with the current source.

公开(公告)号：US09741735B2

公开(公告)日：2017-08-22

申请号：US14993485

申请日：2016-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Wook Lee ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Seunghyun Lim

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/42348

Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

公开(公告)号：US20220116564A1

公开(公告)日：2022-04-14

申请号：US17470187

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEHWA PAIK ,  Jaehong Kim ,  Jinwoo Kim ,  Seunghyun Lim ,  Sanghyun Cho

IPC: H04N5/3745 ,  H04N5/369 ,  H04N5/376 ,  H04N5/363 ,  H03M1/56

Abstract: An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.

公开(公告)号：US09831265B2

公开(公告)日：2017-11-28

申请号：US15165135

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nambin Kim ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Changsub Lee ,  Seunghyun Lim ,  Sunghoi Hur

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

公开(公告)号：US11627276B2

公开(公告)日：2023-04-11

申请号：US17470187

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehwa Paik ,  Jaehong Kim ,  Jinwoo Kim ,  Seunghyun Lim ,  Sanghyun Cho

IPC: H04N5/378 ,  H04N5/369 ,  H04N5/363 ,  H04N5/376 ,  H03M1/56

Abstract: An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.

公开(公告)号：US20240107195A1

公开(公告)日：2024-03-28

申请号：US18240483

申请日：2023-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heesung Shim ,  Seungsik Kim ,  Jaekyu Lee ,  Seunghyun Lim ,  Sungjae Jun

IPC: H04N25/771 ,  H04N23/667 ,  H04N25/531 ,  H04N25/532

CPC classification number: H04N25/771 ,  H04N23/667 ,  H04N25/531 ,  H04N25/532

Abstract: An image sensor comprising a pixel array in which a plurality of pixels are arranged and a row driver . Each of the pixel includes a photodiode, a transfer transistor for transferring photocharges of the photodiode to a floating diffusion node (FD), a conversion gain control transistor, a first source follower for amplifying and outputting the voltage of the FD to a first node, a precharge selection transistor connected between the first node and a second node, a first capacitor, a first sampling transistor connected between the second node and the first capacitor, a second capacitor, a second sampling transistor connected between the second node and the second capacitor, a second source follower for amplifying a voltage of the second node, a first selection transistor connected between the second source follower and a column line, and a second selection transistor connected between the first node and the column line.

公开(公告)号：US20230345152A1

公开(公告)日：2023-10-26

申请号：US18062853

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwa Paik ,  Cyuyeol Rhee ,  Kyungil Kim ,  Jaehong Kim ,  Jinwoo Kim ,  Seunghyun Lim ,  Sanghyun Cho

IPC: H04N25/78 ,  H04N25/709

CPC classification number: H04N25/78 ,  H04N25/709

Abstract: An analog-to-digital converting circuit includes a first amplifier configured to output a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier configured to generate a second output signal based on the first output signal. The second amplifier includes a first transistor configured to provide a power supply voltage to a first output node in response to the first output signal, a second transistor connected with a capacitor through a bias node, wherein the second transistor is configured to turn on in response to an auto-zero signal, a current source connected with the first transistor through the first output node, the current source configured to generate a power current based on a voltage level of the bias node, and a third transistor connected with the current source.