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1.发明公开公开(公告)号：US20230221747A1
公开(公告)日：2023-07-13
申请号：US18149278
申请日：2023-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehoon LEE , Yong LIM , Seunghyun OH
Abstract: A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.
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公开(公告)号：US20220407538A1
公开(公告)日：2022-12-22
申请号：US17705776
申请日：2022-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehoon LEE , Yong LIM , Seunghyun OH
Abstract: An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.
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公开(公告)号：US20210036722A1
公开(公告)日：2021-02-04
申请号：US16767225
申请日：2019-01-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wonsub LIM , Seunghyun OH , Hyoseok NA , Dongil YANG
Abstract: Disclosed is an electronic device. Other various embodiments as understood from the specification are also possible. The electronic device may include an antenna, a communication module including a transceiver, and a control circuit. The control circuit may be configured to radiate a first signal generated from the transceiver through the antenna, to obtain at least part of a second signal obtained by combining a forward signal delivered from the communication module to the antenna and a reverse signal reflected from the antenna, and to determine a reflection coefficient for the antenna based on at least part of the first signal and at least part of the second signal.
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4.发明公开公开(公告)号：US20230170912A1
公开(公告)日：2023-06-01
申请号：US17964377
申请日：2022-10-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Baekmin LIM , Seungjin KIM , Seunghyun OH
CPC classification number: H03L7/1976 , H03L7/081 , H03L7/093
Abstract: A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.
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公开(公告)号：US20230122691A1
公开(公告)日：2023-04-20
申请号：US17865811
申请日：2022-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gyusik KIM , Seungjin KIM , Seunghyun OH
Abstract: A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.
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Patent Agency Ranking
公开(公告)号：US20220407459A1
公开(公告)日：2022-12-22
申请号：US17845378
申请日：2022-06-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehong JUNG , Seunghyun OH , Jinhyeon LEE , Gihyeok HA , Seungjin KIM , Joomyoung KIM , Yelim YOUN , Jaehoon LEE
Abstract: A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.
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公开(公告)号：US20220376698A1
公开(公告)日：2022-11-24
申请号：US17560400
申请日：2021-12-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngsea CHO , Wan KIM , Jiseon PAEK , Seunghyun OH
Abstract: Provided are an analog-to-digital converter and/or an operating method thereof. The analog-to-digital converter includes a sample/hold circuit, a digital-to-analog converter, a comparing circuit, and a control logic circuit, wherein the digital-to-analog converter includes a first capacitor connected to a first comparison node and a first filtering node, a first reference voltage switch connected to the first filtering node and connected to a first delivery node or a first transmission node, a first pre-charge switch connected to the first filtering node or the first delivery node, and a first pre-charge capacitor connected to the first pre-charge switch and a ground voltage.
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公开(公告)号：US20180054196A1
公开(公告)日：2018-02-22
申请号：US15679550
申请日：2017-08-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongil YANG , Wonsub LIM , Daeyoung KIM , Sunah PARK , Seunghyun OH
CPC classification number: H03K17/962 , G01R1/025 , G06F1/1626 , G06F1/1684 , H01Q1/243 , H03K2217/94089 , H03K2217/960775 , H04B1/006 , H04B1/0458 , H04B1/3838 , H04B1/385 , H04B5/0031 , H04B5/0056 , H04M1/72569 , H04W4/80 , H04W12/06 , H04W52/0254 , Y02D70/00 , Y02D70/1242 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/164 , Y02D70/166 , Y02D70/168 , Y02D70/20 , Y02D70/26 , Y02D70/42
Abstract: An electronic device and a method of grip recognition of the electronic device are provided. The electronic device includes an antenna, a radio communication device having a coupler, a memory, and a processor which is electrically connected to the radio communication device and the memory, wherein the memory includes instructions, executable by the processor, wherein the processor is configured to detect a first signal being transmitted and a second signal being received through the antenna using the coupler, calculate a reflection coefficient of the antenna based on the first signal and the second signal, determine a signal magnitude and a phase corresponding to the reflection coefficient, and determine whether the electronic device is being gripped based on the signal magnitude and the phase.
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9.发明公开公开(公告)号：US20240171186A1
公开(公告)日：2024-05-23
申请号：US18422192
申请日：2024-01-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsea CHO , Wan KIM , Jiseon PAEK , Seunghyun OH
IPC: H03M1/06
CPC classification number: H03M1/0617 , H03M1/66
Abstract: A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.
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公开(公告)号：US20220094302A1
公开(公告)日：2022-03-24
申请号：US17340593
申请日：2021-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehong JUNG , Wonkang KIM , Seungjin KIM , Seunghyun OH
Abstract: A crystal oscillator reducing phase noise and a semiconductor chip including the same are provided. The crystal oscillator includes a transconductance circuit electrically connected to a crystal, a load capacitor connected to the transconductance circuit, a feedback resistance circuit connected between an input terminal of the transconductance circuit and an output terminal of the transconductance circuit, the feedback resistance circuit configured to provide a feedback resistance, and a variable resistance controller configured to generate a resistance control signal for controlling the feedback resistance, the resistance control signal causing the feedback resistance to have a first value in a first period and a second value in a second period, the first value being less than the second value, the first period corresponding to a first portion of a cycle of the clock signal, and the second period corresponding to a second portion of the cycle different from the first portion.
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