公开(公告)号：US20240422966A1

公开(公告)日：2024-12-19

申请号：US18736748

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Hyesung Park ,  Seungji Kang ,  Seongeun Kim ,  Dongwon Lee ,  Juyeon Han

IPC: H10B12/00 ,  H01L23/528

Abstract: An integrated circuit device includes a substrate having a memory cell area and a peripheral circuit area extending around the memory cell area, cell transistors in the memory cell area, and a peripheral circuit transistor in the peripheral circuit area. The device further includes: a capacitor structure including lower electrodes on the cell transistors, a dielectric layer on a surface of the lower electrodes, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer on the metal plate layer in the memory cell area and on the peripheral circuit transistor in the peripheral circuit area; and an etch stop pattern in the interlayer insulating layer at a boundary portion of the memory cell area and the peripheral circuit area. The etch stop pattern is spaced laterally from a sidewall of the metal plate layer and extends vertically.