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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160365356A1

    公开(公告)日：2016-12-15

    申请号：US15248564

    申请日：2016-08-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Won-Seok JUNG ,  Changseok KANG ,  Seungwoo PAEK ,  Inseok YANG ,  Kyungjoong JOO

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

    Abstract translation: 半导体器件包括衬底，堆叠结构，外围栅极结构和残余间隔物。 衬底包括电池阵列区域和外围电路区域。 堆叠结构设置在电池阵列区域上，具有交替堆叠的电极和绝缘层。 外围栅极结构设置在外围电路区域上，在一个方向上彼此间隔开并且具有设置在基板上的周边栅极图案，以及设置在外围栅极图案的侧壁上的外围栅极间隔件。 剩余间隔物设置在外围栅极结构的侧壁上，具有堆叠的牺牲图案和绝缘图案。 绝缘图案包括与堆叠结构的绝缘层基本相同的材料。

    DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS
    2.
    发明申请
    DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS 有权

    公开(公告)号：US20210407968A1

    公开(公告)日：2021-12-30

    申请号：US17315716

    申请日：2021-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunji KIM ,  Seungwoo PAEK ,  Byungkyu KIM ,  Sangjun PARK ,  Sungdong CHO

    IPC: H01L25/065 ,  H01L23/00 ,  H01L29/423 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L23/498 ,  H01L23/538

    Abstract: A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer.

    SEMICONDUCTOR CHIP STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR CHIP STRUCTURE 有权

    公开(公告)号：US20220285208A1

    公开(公告)日：2022-09-08

    申请号：US17453504

    申请日：2021-11-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangjun PARK ,  Byungkyu KIM ,  Eunji KIM ,  Seungwoo PAEK ,  Sungdong CHO

    IPC: H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240407171A1

    公开(公告)日：2024-12-05

    申请号：US18672106

    申请日：2024-05-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： PYEONGWOO KIM ,  Changsup LEE ,  Seungwoo PAEK ,  Yunsun JANG

    IPC: H10B43/40 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

    Abstract: A semiconductor device including a peripheral circuit structure; and a cell structure stacked on the peripheral circuit structure and including a cell region, a connection region, and a peripheral circuit connection region, wherein the cell structure includes gate electrodes spaced apart from one another in a vertical direction in the cell region; a channel structure extending in the vertical direction through the gate electrodes, in the cell region, and including a first end and a second end opposite to the first end, the first end being proximate to the peripheral circuit structure; an insulating wall extending in the vertical direction at a boundary between the cell region and the connection region; and a common source layer connected to the second end of the channel structure in the cell region and having a portion arranged on a sidewall of the insulating wall.

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