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公开(公告)号：US20210200513A1
公开(公告)日：2021-07-01
申请号：US16909214
申请日：2020-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng KANG , Sukhan LEE
Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.
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公开(公告)号：US20240370227A1
公开(公告)日：2024-11-07
申请号：US18774303
申请日：2024-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng KANG , Sukhan LEE
Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.
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公开(公告)号：US20220100467A1
公开(公告)日：2022-03-31
申请号：US17547991
申请日：2021-12-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng KANG , Seongil O
Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.
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公开(公告)号：US20190122100A1
公开(公告)日：2019-04-25
申请号：US16160444
申请日：2018-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng KANG , Seungwon LEE
Abstract: Provided is a processor implemented method that includes performing training or an inference operation with a neural network by obtaining a parameter for the neural network in a floating-point format, applying a fractional length of a fixed-point format to the parameter in the floating-point format, performing an operation with an integer arithmetic logic unit (ALU) to determine whether to round off a fixed point based on a most significant bit among bit values to be discarded after a quantization process, and performing an operation of quantizing the parameter in the floating-point format to a parameter in the fixed-point format, based on a result of the operation with the ALU.
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公开(公告)号：US20240419612A1
公开(公告)日：2024-12-19
申请号：US18819544
申请日：2024-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hak-soo YU , Shinhaeng KANG , Yuhwan RO
Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.
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Patent Agency Ranking
公开(公告)号：US20230094148A1
公开(公告)日：2023-03-30
申请号：US17879523
申请日：2022-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sukhan LEE , Shinhaeng KANG , Kyomin SOHN
IPC: G06F3/06
Abstract: A memory device for reducing timing parameters and power consumption for an internal processing operation and a method of implementing the same are provided. The memory device includes a memory cell array, a processing-in-memory (PIM) circuit configured to perform a processing operation and a control logic circuit configured to control a normal mode and an internal processing mode. The control logic circuit writes an operation result obtained by the processing operation of the PIM circuit in the internal processing mode in the memory cell array and provides read data read from the memory cell array to the PIM circuit.
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公开(公告)号：US20230042954A1
公开(公告)日：2023-02-09
申请号：US17965351
申请日：2022-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng KANG , Sukhan LEE
Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.
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8.发明申请公开(公告)号：US20220318165A1
公开(公告)日：2022-10-06
申请号：US17845441
申请日：2022-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng KANG , Sukhan LEE
Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.
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公开(公告)号：US20240419445A1
公开(公告)日：2024-12-19
申请号：US18814125
申请日：2024-08-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yuhwan RO , Shinhaeng KANG , Seongil O , Seungwoo SEO
Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.
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10.发明公开公开(公告)号：US20240036820A1
公开(公告)日：2024-02-01
申请号：US18486518
申请日：2023-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng KANG , Seongil O
CPC classification number: G06F7/48 , G06F13/16 , G11C7/1048 , G11C2207/2272
Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.
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